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參數資料
| 型號： | IS61LV6432 |
| 英文描述： | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| 中文描述： | 64K的× 32 SYNCHRONOU擰管道靜態RAM |
| 文件頁數： | 4/16頁 |
| 文件大?。?/td> | 487K |
| 代理商： | IS61LV6432 |
IS61LV6432
4
Integrated Circuit Solution Inc.
SSR005-0B
TRUTH TABLE
Address
Used
Operation
CE1
CE2
CE3
ADSP ADSC
ADV WRITE
OE
DQ
Deselected, Power-down
None
H
X
X
X
L
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
L
X
X
X
X
High-Z
Deselected, Power-down
None
L
L
X
H
L
X
X
X
High-Z
Deselected, Power-down
None
L
X
H
H
L
X
X
X
High-Z
Read Cycle, Begin Burst External
L
H
L
L
X
X
X
L
Q
Read Cycle, Begin Burst External
L
H
L
L
X
X
X
H
High-Z
Write Cycle, Begin Burst External
L
H
L
H
L
X
L
X
D
Read Cycle, Begin Burst External
L
H
L
H
L
X
H
L
Q
Read Cycle, Begin Burst External
L
H
L
H
L
X
H
H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
D
Read Cycle, Suspend Burst Current
X
X
X
H
H
H
H
L
Q
Read Cycle, Suspend Burst Current
X
X
X
H
H
H
H
H
High-Z
Read Cycle, Suspend Burst Current
H
X
X
X
H
H
H
L
Q
Read Cycle, Suspend Burst Current
H
X
X
X
H
H
H
H
High-Z
Write Cycle, Suspend Burst Current
X
X
X
H
H
H
L
X
D
Write Cycle, Suspend Burst Current
H
X
X
X
H
H
L
X
D
Notes:
1. All inputs except
OE
must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care.
WRITE
=L means any one or more byte write enable signals (
BW
1-
BW
4) and
BWE
are LOW or
GW
is
LOW.
WRITE
=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation,
OE
must be HIGH before the input data required setup time and held
HIGH throughout the input data hold time.
5.
ADSP
LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or
more byte write enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of clock.
PARTIAL TRUTH TABLE
Function
GW
BWE
BW1
BW2
BW3 BW4
READ
H
H
X
X
X
X
READ
H
X
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE All Bytes
X
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
相關PDF資料 |
PDF描述 |
|---|---|
| IS61LV6432-117TQ | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-8PQI | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61NW6432 | 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE |
| IS61NW6432-5PQ | 64K x 32 SYNCHRONOUS STATIC RAM WITH NO-WAIT STATE BUS FEATURE |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| IS61LV6432-117PQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117PQI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117TQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-117TQI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
| IS61LV6432-133PQ | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:64K x 32 SYNCHRONOUS PIPELINE STATIC RAM |
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