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參數(shù)資料
| 型號(hào)： | IS61SF6432 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 32 Synchronous Flow-Through SRAM(64K x 32 同步流通結(jié)構(gòu)靜態(tài)RAM) |
| 中文描述： | 64K的× 32同步流通過的SRAM（64K的× 32同步流通結(jié)構(gòu)靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 215K |
| 代理商： | IS61SF6432 |
IS61SF6432
IS61SF6432
64K x 32 SYNCHRONOUS
FLOW-THROUGH STATIC RAM
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
SR012-0C
06/01/98
1
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc.
FEATURES
Fast access time: 9 ns, 10 ns
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control
using MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
Power-down control by ZZ input
JEDEC 100-Pin TQFP and PQFP package
Single +3.3V power supply
Two Clock enables and one Clock disable to
eliminate multiple bank bus contention.
Control pins mode upon power-up:
– FT in pipeline mode
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
Q
or V
CCQ
to alter their power-up state
Industrial temperature available
DESCRIPTION
The
ISSI
IS61SF6432 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the Pentium, 680X0,
and PowerPC microprocessors. It is organized as 65,536
words by 32 bits, fabricated with
ISSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-DQ8,
BW2
controls DQ9-DQ16,
BW3
controls DQ17-DQ24,
BW4
controls DQ25-DQ32, conditioned
by
BWE
being LOW. A LOW on
GW
input would cause all bytes
to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61SF6432 and controlled by the
ADV
(burst
address advance) input pin.
Asynchronous signals include output enable (
OE
), sleep mode
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
Q
, on MODE pin selects LINEAR Burst. A V
CCQ
(or no connect) on MODE pin selects INTERLEAVED Burst.
ADVANCE INFORMATION
JUNE 1998
ISSI
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