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參數(shù)資料
| 型號： | IS61SP12832 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 128K x 32 Synchronous Pipelined SRAM(128K x 32 同步流水線靜態(tài)RAM) |
| 中文描述： | 128K的同步流水線× 32的SRAM（128K的× 32同步流水線靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 125K |
| 代理商： | IS61SP12832 |
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00B
04/04/00
1
IS61SP12832
IS61SP12836
128K x 32, 128K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
ISSI
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1998, Integrated Silicon Solution, Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control using
MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +3.3V, +10%, –5% power supply
Power-down snooze mode
DESCRIPTION
The
ISSI
IS61SP12832 and IS61SP12836 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 131,072
words by 32 bits and 36 bits, fabricated with
ISSI
's ad-
vanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All syn-
chronous inputs pass through registers controlled by a
positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls
DQc,
BW4
controls DQd, conditioned by
BWE
being
LOW. A LOW on
GW
input would cause all bytes to be
written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
PRELIMINARY INFORMATION
MARCH 2000
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-200
3.1
5
200
-166
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-5
5
10
100
Units
ns
ns
MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS61SP12836 | 128K x 36 Synchronous Pipelined SRAM(128K x 36 同步流水線靜態(tài)RAM) |
| IS61SP25616 | 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP25616-133B | 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP25616-133TQ | 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM |
| IS61SP25616-133TQI | 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS61SP12836-133B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-133TQ-T | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP T/R |
| IS61SP12836-166B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-200B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP6464-100PQ | 制造商:Integrated Silicon Solution Inc 功能描述: |
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