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參數資料
| 型號： | IS61SP25616-133TQ |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM |
| 中文描述： | 256K X 16 CACHE SRAM, 4 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 1/15頁 |
| 文件大?。?/td> | 120K |
| 代理商： | IS61SP25616-133TQ |
IS61SP25616
IS61SP25618
256K x 16, 256K x 18 SYNCHRONOUS
PIPELINED STATIC RAM
ISSI
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
Internal self-timed write cycle
Individual Byte Write Control and Global Write
Clock controlled, registered address, data and
control
Pentium or linear burst sequence control using
MODE input
Three chip enables for simple depth expansion
and address pipelining
Common data inputs and data outputs
JEDEC 100-Pin TQFP and
119-pin PBGA package
Single +3.3V, +10%, -5% power supply
Power-down snooze mode
DESCRIPTION
The
ISSI
IS61SP25616 and IS61SP25618 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 262,144
words by 16 bits and 18 bits, fabricated with
ISSI
's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ1-8,
BW2
controls DQ9-16, conditioned
by
BWE
being LOW. A LOW on
GW
input would cause all
bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
APRIL 2001
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-166
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-5
5
10
100
Units
ns
ns
MHz
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| IS61SP25616-133TQI | 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM |
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| IS61SP25616-166B | Octal D-Type Edge-Triggered Flip-Flops with 3-State Outputs 20-TSSOP -40 to 85 |
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