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參數資料
| 型號： | ISD5116SERIES |
| 英文描述： | Single-Chip Voice Record/Playback Device with Digital Memory Capability |
| 中文描述： | 單芯片語音記錄/回放和數字記憶能力的裝置 |
| 文件頁數： | 24/81頁 |
| 文件大小： | 2441K |
| 代理商： | ISD5116SERIES |
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ISD5116
4.
Power down the FILTER stage
—
Bit FLPD controls the power up state of the FILTER stage in
the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
5.
Power down the AGC amplifier
—
Bit AGPD controls the power up state of the AGC amplifier.
This is bit D0 in CFG1 and should be set to a ONE to power down this stage.
6.
Don’t Care bits
—
The following stages are not used in Feed Through Mode. Their bits may be
set to either level. In this example, we will set all the following bits to a ZERO. (a). Bit INS0, bit
D9 of CFG0 controls the Input Source Mux. (b). Bits AXG0 and AXG1 are bits D11 and D12
respectively in CFG0. They control the AUX IN amplifier gain setting. (c). Bits FLD0 and FLD1
are bits D2 and D3 respectively in CFG1. They control the sample rate and filter band pass
setting. (d). Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX. (e). Bits S1S0 and S1S1
are bits D9 and D10 of CFG1. They control the SUM1 MUX. (f). Bits VOL0, VOL1 and VOL2
are bits D11, D12 and D13 of CFG1. They control the setting of the Volume Control. (g). Bits
VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control MUX.
The end result of the above set up is
CFG0=0100 0100 0000 1011 (hex 440B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
Since both registers are being loaded, CFG0 is loaded, followed by the loading of CFG1. These two
registers must be loaded in this order. The internal set up for both registers will take effect synchro-
nously with the rising edge of SCL.
7.3.8. Call Record
The call record mode adds the ability to record an incoming phone call. In most applications, the
ISD5116 would first be set up for Feed Through Mode as described above. When the user wishes to
record the incoming call, the setup of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz sample rate during recording.
The block diagram of the ISD5116 shows that the Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, THE
FILTER MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed
Through Mode has already powered up the ANA IN amp so we only need to power up and enable the
path to the Multilevel Storage array from that point:
1. Select the ANA IN path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the
SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set to the
state where both D9 and D10 are ZERO to select the ANA IN path.
2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISD5116SI | 功能描述:IC VOICE REC/PL 8-16MN IN 28SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SIR | 功能描述:IC VOICE REC/PL 8-16MN IN 28SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SY | 功能描述:IC VOICE REC/PLAY 8-16MN 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SYI | 功能描述:IC VOICE REC/PLAY 8-16MN 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SYIR | 功能描述:IC VOICE REC/PLAY 8-16MN 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
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