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參數資料
| 型號： | ISD5116SERIES |
| 英文描述： | Single-Chip Voice Record/Playback Device with Digital Memory Capability |
| 中文描述： | 單芯片語音記錄/回放和數字記憶能力的裝置 |
| 文件頁數： | 26/81頁 |
| 文件大小： | 2441K |
| 代理商： | ISD5116SERIES |
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ISD5116
CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the
INPUT SOURCE MUX (only) path.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the
state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the
SUM1 SUMMING amplifier path.
5. Power up the LOW PASS FILTER
—
Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier
—
Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to
select the LOW PASS FILTER (only) path.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
Only those portions necessary for this mode are powered up.
7.3.10. Memo and Call Playback
This mode sets the chip up for local playback of messages recorded earlier. The playback path is from
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage.
From there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX,
through the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are
driving a piezo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages
will be powered down.
1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX
—
Bit FLS0, the
state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the
MULTILEVEL STORAGE ARRAY.
2. Power up the LOW PASS FILTER
—
Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to
select the LOW PASS FILTER (only) path.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ISD5116SI | 功能描述:IC VOICE REC/PL 8-16MN IN 28SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SIR | 功能描述:IC VOICE REC/PL 8-16MN IN 28SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SY | 功能描述:IC VOICE REC/PLAY 8-16MN 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SYI | 功能描述:IC VOICE REC/PLAY 8-16MN 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
| ISD5116SYIR | 功能描述:IC VOICE REC/PLAY 8-16MN 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 語音錄制和重放 系列:ISD5100 標準包裝:14 系列:- 接口:串行 濾波器通頻帶:1.7kHz 持續時間:8 ~ 32 秒 安裝類型:通孔 封裝/外殼:28-DIP（0.300"，7.62mm） 供應商設備封裝:28-PDIP 其它名稱:90-21300+000 |
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