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參數資料
| 型號： | ISL58328CIZ-T7 |
| 廠商： | Intersil |
| 文件頁數： | 10/14頁 |
| 文件大小： | 380K |
| 描述： | IC LASER PWR MONITOR 5V 9CSP |
| 標準包裝： | 1 |
| 傳感器類型： | 光學 |
| 輸出類型： | 電壓 |
| 其它名稱： | ISL58328CIZ-T7DKR ISL58328CIZ-T7TRDKR ISL58328CIZ-T7TRDKR-ND |
ISL58328
10
FN6329.2
July 29, 2013
Register Description
1Ah
ST_RED
st_en_red
st_time_red[2:0]
x
st_mag_red[2:0]
00h
RW
1Bh
ST_GREEN
st_en_green
st_time_green[2:0]
x
st_mag_green[2:0]
00h
RW
1Ch
TIA_GAIN
x
x
x
x
tia_h[1:0]
tia_l[1:0]
00h
RW
1Dh
reserved
1Eh
ST_BLUE
st_en_blue
st_time_blue[2:0]
x
st_mag_blue[2:0]
00h
RW
Note: All gain registers in this table can be used for any wavelength in spectral range from 390nm to 1000nm, not limited to wavelengths specified.
Register Map (Continued)
ADDR
NAME
b7
b6
b5
b4
b3
b2 b1
b0
DEFAULT
ACCESS
TABLE 3. ID0 (addr = 00h)
REGISTER
DESCRIPTION
ID0
Device ID, read only, code = 28h
TABLE 4. ID1 (addr = 01h)
REGISTER
DESCRIPTION
DEVICE OPTION
Device option code, read only,
code = E0h
DEVICE VERSION
Device version code, read only, code = 0h
TABLE 5. DSR (addr = 03h)
REGISTER
DESCRIPTION
DSR (Note 7) Device selection code, used for Intersil universal Serial
Interface protocol, code = 43h
NOTE:
7. DSR register is to allow multiple devices to share same the SPI
interface. Each device on the SPI interface bus has its own DSR value,
like a device address in I
2
C protocol. Master sends DSR to the SPI
bus, only one device with a matched DSR will response to the
following commands and data, remaining devices on the bus will
ignore commands and data; pull the interface to Hi-Z. For more
information please contact Intersil for Universal Serial Interface
Specification document.
TABLE 6. CONTROL (addr = 10h)
REGISTER
DESCRIPTION
h/l
Bit [7]
HIGH gain or LOW Gain channels selection. Used in
conjunction with HL pin.
1b: HIGH Gain channel
0b: LOW Gain channel
Default: 0b
deglitch
Bit [6]
1b: Enable serial interface deglitch function
0b: Disable serial interface deglitch function
Default: 0b
blue
Bit [5]
1b: Device works in blue mode
(regardless of red/green bit setting)
0b: Device works in either RED or GREEN mode, depends
on red/green register bit setting
Default: 0b
red/green
Bit [4]
0b: GREEN
1b: RED
Default: 0b (GREEN mode)
test_en
Bit [3]
To enable a chip test function
(for Intersil internal use only)
1b: Enable test function
0b: Disable test function
Default: 0b
chip_en
Bit [0]
To enable or disable ISL58328. When disabled all
outputs are in Hi-Z
1b: enable
0b: disable (SLEEP mode)
TABLE 7. B_GAIN0 (addr = 11h)
REGISTER
DESCRIPTION
blue_h[3: 0]
Bits [7:4]
Lower 4 bits of blue light HIGH Gain channel fine gain
control
blue_l[3: 0]
Bits [3:0]
Lower 4 bits of blue light LOW Gain channel fine gain
control
TABLE 8. B_H_GAIN (addr = 12h)
REGISTER
DESCRIPTION
blue_h[11:4]
Bits [7:0]
High 8 bits of blue light HIGH Gain channel fine gain
control
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