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參數(shù)資料
| 型號： | ISL58328CIZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 380K |
| 描述： | IC LASER PWR MONITOR 5V 9CSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感器類型： | 光學(xué) |
| 輸出類型： | 電壓 |
| 其它名稱： | ISL58328CIZ-T7DKR ISL58328CIZ-T7TRDKR ISL58328CIZ-T7TRDKR-ND |
ISL58328
5
FN6329.2
July 29, 2013
Sensitivity
V
DD
= 5.0V, T
A
= +25癈 unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
Gain
00
TIA Lowest Gain
0dB fine gain adjustment, 7FFh
Differential output
350
450
550
mV/礎(chǔ)
Gain
01
TIA 2nd Lowest Gain
0dB fine gain adjustment, 7FFh
Differential output
700
890
1110
mV/礎(chǔ)
Gain
10
TIA 2nd Highest Gain
0dB fine gain adjustment, 7FFh
Differential output
1400
1790
2170
mV/礎(chǔ)
Gain
11
TIA Highest Gain
0dB fine gain adjustment, 7FFh
Differential output
3700
4850
6020
mV/礎(chǔ)
Gain
Fine_MAX
Maximum Fine Gain
for both HIGH Gain and LOW Gain channels
Compared to 0dB fine gain setting, 7FFh
19
dB
Gain
Fine_MIN
Minimum Fine Gain
for both HIGH Gain and LOW Gain channels
Compared to 0dB fine gain setting, 7FFh
-5.5
dB
Current to Optical conversion: Optical sensitivity is not tested in production. Gain parameters were obtained using input test currents. Following factors
are used to convert current to optical power.
I2O
450nm
Current to Optical conversion
(450nm)
Bench data; measured on typical devices
0.27
礎(chǔ)/礧
I2O
530nm
Current to Optical conversion
(530nm)
Bench data; measured on typical devices
0.26
礎(chǔ)/礧
I2O
640nm
Current to Optical conversion
(640nm)
Bench data; measured on typical devices
0.38
礎(chǔ)/礧
Serial Interface AC Performance V
DD
= 5.0V, T
A
= +25癈 unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
F
SER1
SCLK Operating Range
Deglitch disable(CONTROL[6]=0)
50
MHz
F
SER2
SCLK Operating Range
Deglitch enable(CONTROL[6]=1)
2
MHz
t
EH
SEN H Time
320
ns
t
EL
SEN L Time
40
ns
t
ERSR
SEN Rising Edge to the First SCLK Rising
Edge
10
ns
t
CDS
SDIO Set Up Time
10
ns
t
CDH
SDIO Hold Time
10
ns
t
SREF
Last SCLK Rising Edge to SEN Falling Edge
10
ns
t
CC
SCLK Cycle Time
20
ns
Duty
SCLK H Duty Cycle
50
%
t
CDD
SDIO Output Delay
4
ns
t
EDH
SDIO Output Hold Time
2
ns
INPUT
LEAKAGE
Input Leakage for SCLK, SDATA, and SEN
pin
-10
10
礎(chǔ)
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