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參數資料
型號: ISP1130DL
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Serial Bus compound hub with integrated keyboard controller
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝: PLASTIC, SSOP-56
文件頁數: 36/68頁
文件大小: 1786K
代理商: ISP1130DL
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
36 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
10.3.1
Program Status Word register (PSW)
The PSW register of the 80C51 is bit-addressable. The names and functions of the
bits are shown in
Table 48
and
Table 49
.
[1]
All bits are individually addressable.
Table 47: SFR memory map
Address
range
(Hex)
F8 to FF
F0 to F7
E8 to EF
E0 to E7
D8 to DF
D0 to D7
C8 to CF
C0 to C7
B8 to BF
B0 to B7
A8 to AF
A0 to A7
98 to 9F
90 to 97
88 to 8F
80 to 87
Offset
0
1
2
3
4
5
6
7
WDTKEY
WDT
B
ACC
I2C0CON
PSW
I2C0STA
I2C0DAT
I2C0ADR
USBCON
IP
P3
IE
P2
USBCONA
P1
TCON
P0
TMOD
SP
TL0
DPL
TL1
DPH
TH0
TH1
PCON
Table 48: PSW register: bit allocation
7
6
CY
AC
5
4
3
2
1
-
0
P
F0
RS1
RS0
OV
Table 49: PSW register: bit description
Bit
[1]
Symbol
PSW.7
CY
PSW.6
AC
Description
carry flag; receives carry out from bit 7 of ALU operands
auxiliary carry flag; receives carry out from bit 3 of addition
operands
flag 0; general purpose status flag
register bank selector bit 1; see
Table 50
register bank selector bit 0; see
Table 50
overflow flag; set by arithmetic operations
user-definable general purpose flag
parity flag, indicating the number of ‘1’ bits in the accumulator
(logic 0 = even, logic 1 = odd); refreshed by hardware upon each
instruction cycle
PSW.5
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0
F0
RS1
RS0
OV
-
P
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