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參數資料
型號: ISP1130DL
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Serial Bus compound hub with integrated keyboard controller
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝: PLASTIC, SSOP-56
文件頁數: 47/68頁
文件大小: 1786K
代理商: ISP1130DL
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
47 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
11.1 Protocol
The I
2
C-bus protocol defines the following conditions:
Bus free
: both SDA and SCL are HIGH
START
: a HIGH-to-LOW transition on SDA, while SCL is HIGH
STOP
: a LOW-to-HIGH transition on SDA, while SCL is HIGH
Data valid
: after a START condition, data on SDA are stable during the HIGH
period of SCL; data on SDA may only change while SCL is LOW.
Each device on the I
2
C-bus has a unique slave address, which the master uses to
select a device for access.
The master starts a data transfer using a START condition and ends it by generating
a STOP condition. Transfers can only be initiated when the bus is free. The receiver
must acknowledge each byte by means of a LOW level on SDA during the ninth clock
pulse on SCL.
For detailed information please consult The I
2
C-bus and how to use it, order number
9398 393 40011.
11.2 Hardware connections
Via the I
2
C-bus interface the ISP1130 can be connected to an external EEPROM
(PCF8582 or equivalent). The hardware connections are shown in
Figure 8
.
The SCL and SDA pins are multiplexed with pins MX3 and MX4 respectively. Pin
MEMSEL/UPGL can be used as a chip select output to select external devices, such
as smart card readers, UARTs, etc.
The slave address which ISP1130 uses to access the EEPROM is 1010000B. Page
mode addressing is not supported, so pins A0, A1 and A2 of the EEPROM must be
connected to GND (logic 0).
Fig 8.
EEPROM connection diagram.
idth
MGS808
MX4/SDA
MX3/SCL
A1
A2
A0
SDA
SCL
VDD
RP
RP
VDD
ISP1130
USB HUB
PCF8582
EEPROM
or
equivalent
I
2
C-bus
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