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參數資料
型號: ISP1161A1
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus single-chip host and device controller
中文描述: 通用串行總線的單芯片主機和設備控制器
文件頁數: 44/127頁
文件大小: 2762K
代理商: ISP1161A1
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
44 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
When the DMA controller terminates the DMA transfer by asserting EOT and
Auto-reload mode is off, the buffer is also cleared (even if not all data are read) and
the DMA handler is disabled automatically. For the next DMA transfer, the DMA
controller as well as the DMA handler must be re-enabled. However in Auto-reload
mode, the DMA handler will automatically restart by reasserting the DREQ2 line,
without any loss of data.
11.3 Endpoint descriptions
11.3.1
Endpoints with programmable FIFO size
Each USB device is logically composed of several independent endpoints. An
endpoint acts as a terminus of a communication flow between the host and the
device. At design time each endpoint is assigned a unique number (endpoint
identifier, see
Table 7
). The combination of the device address (given by the host
during enumeration), the endpoint number and the transfer direction allows each
endpoint to be uniquely referenced.
The ISP1161 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 configurable
endpoints, which can be individually defined as interrupt/bulk/isochronous, IN or OUT.
Each enabled endpoint has an associated FIFO, which can be accessed either via
the parallel I/O interface or via DMA.
11.3.2
Endpoint access
Table 7
lists the endpoint access modes and programmability. All endpoints support
I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is
selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Configuration
Register. A detailed description of the DMA operation is given in
Section 12
.
Table 7:
Endpoint
identifier
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Endpoint access and programmability
FIFO size (bytes)
Double
buffering
no
no
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
I/O mode
access
yes
yes
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
DMA mode
access
no
no
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
supported
Endpoint type
64 (fixed)
64 (fixed)
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
control OUT
[1]
control IN
[1]
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
programmable
相關PDF資料
PDF描述
ISP1161A1BD Universal Serial Bus single-chip host and device controller
ISP1161A1BM Universal Serial Bus single-chip host and device controller
ISP1161BD Full-speed Universal Serial Bus single-chip host and device controller
ISP1161BM Full-speed Universal Serial Bus single-chip host and device controller
ISP1181ABS INDUCTOR 1.0NH +-.3NH FIXED SMD
相關代理商/技術參數
參數描述
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ISP1161A1BD,157 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BDFA 功能描述:IC USB HOST CONTROLLER 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN(6x6) 包裝:* 其它名稱:Q6396337A
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