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參數資料
型號： ISP1161A
廠商： NXP Semiconductors N.V.
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： 全速通用串行總線的單芯片主機和設備控制器
文件頁數： 31/134頁
文件大小： 587K
代理商： ISP1161A
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
31 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The data transfer can be done via the PIO mode or the DMA mode. The data transfer
rate can go up to 15 Mbyte/s. In DMA operation, single-cycle or multi-cycle burst
modes are supported. Multi-cycle burst modes of 1, 4, or 8 cycles per burst is
supported for ISP1161A.
9.4.2
Data organization
PTD data is used for every data transfer between a microprocessor and the USB bus,
and the PTD data resides in the buffer RAM. For an OUT or SETUP transfer, the
payload data is placed just after the PTD, after which the next PTD is placed. For an
IN transfer, RAM space is reserved for receiving a number of bytes that is equal to the
total bytes of the transfer. After this, the next PTD and its payload data are placed
(see
Figure 27
).
Remark:
The PTD is defined for both ATL and ITL type data transfers. For ITL, the
PTD data is put into ITL buffer RAM, and the ISP1161A takes care of the Ping-Pong
action for the ITL buffer RAM access.
The PTD data (PTD header and its payload data) is a structure of DWORD (double-
word or 4-byte) alignment. This means that the memory address is organized in
blocks of 4 bytes. Therefore, the first byte of every PTD and the first byte of every
payload data are located at an address which is a multiple of 4.
Figure 28
illustrates
an example in which the first payload data is 14 bytes long, meaning that the last byte
of the payload data is at the location 15H. The next addresses (16H and 17H) are not
multiples of 4. Therefore, the first byte of the next PTD will be located at the next
multiple-of-four address, 18H.
Fig 27. Buffer RAM data organization.
MGT952
PTD of OUT transfer
RAM buffer
payload data of OUT transfer
PTD of IN transfer
empty space for IN total data
PTD of OUT transfer
payload data of OUT transfer
top
bottom
000H
7FFH
相關PDF資料
PDF描述
ISP1161ABD Full-speed Universal Serial Bus single-chip host and device controller
ISP1161ABM Full-speed Universal Serial Bus single-chip host and device controller
ISP1161 Full-speed Universal Serial Bus single-chip host and device controller
ISP1161A1 Universal Serial Bus single-chip host and device controller
ISP1161A1BD Universal Serial Bus single-chip host and device controller
相關代理商/技術參數
參數描述
ISP1161A1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Serial Bus single-chip host and device controller
ISP1161A1BD 功能描述:IC USB HOST/DEVICE CTRLR 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應商設備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161A1BD,118 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BD,151 功能描述:USB 接口集成電路 USB1.1 HOST &DEVICE RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161A1BD,157 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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