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參數資料
型號: ISP1521BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus hub controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數: 18/53頁
文件大小: 270K
代理商: ISP1521BE
Philips Semiconductors
ISP1521
Hi-Speed USB hub controller
Product data
Rev. 03 — 24 November 2004
18 of 53
9397 750 13702
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.2.2
Architecture of configurable hub descriptors
The configurable hub descriptors can be masked in the internal ROM memory; see
Figure 7
. These descriptors can also be supplied from an external EEPROM or a
microcontroller. The ISP1521 implements both the master and slave I
2
C-bus
controllers. The information from the external EEPROM or the microcontroller is
transferred into the internal RAM during the power-on reset. A signature word is used
to identify correct descriptors. If the signature matches, the content of the RAM is
chosen instead of the ROM.
When the external microcontroller mode is selected and while the external
microcontroller is writing to the internal RAM, any request to configurable descriptors
will be responded to with a Not AcKnowledge (NAK). There is no specified time-out
period for the NAK signal. This data is then passed to the host during the
enumeration process.
The three configuration methods are selected by connecting pins SCL and SDA in the
manner given in
Table 11
.
The I
2
C-bus cannot be shared between the EEPROM and the external microcontroller.
Fig 7.
Configurable hub descriptors.
Table 11:
Configuration method
Internal ROM
External EEPROM
External microcontroller
Configuration method
SCL
ground
2.2 k
to 4.7 k
pull-up
driven LOW by the
microcontroller during reset
SDA
ground
2.2 k
to 4.7 k
pull-up
2.2 k
to 4.7 k
pull-up
MLD711
MICROCONTROLLER
SERIAL EEPROM
MASTER/SLAVE
I
2
C-BUS INTERFACE
signature
match
RAM
(256 bytes)
DESCRIPTOR
GENERATOR
INTERFACE
ROM
(256 bytes)
MUX
HUB CORE
I
2
C-bus
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