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參數資料
型號: ISP1582
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線外設控制器
文件頁數: 34/66頁
文件大小: 325K
代理商: ISP1582
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
34 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Peripheral-to-host (IN endpoint):
After each write action, an internal counter is auto
incremented by two to the next location in the TX FIFO. When all bytes have been
written (FIFO byte count = endpoint MaxPacketSize), the buffer is automatically
validated. The data packet will then be sent on the next IN token. When it is
necessary to validate the endpoint whose byte count is less than MaxPacketSize, it
can be done using the Control Function register (bit VENDP).
Host-to-peripheral (OUT endpoint)
: After each read action, an internal counter is
auto decremented by two to the next location in the RX FIFO. When all bytes have
been read, the buffer contents are automatically cleared. A new data packet can then
be received on the next OUT token. The buffer contents can also be cleared through
the Control Function register (bit CLBUF), when it is necessary to forcefully clear the
contents.
Remark:
The buffer can be automatically validated or cleared by using the Buffer
Length register (see
Table 37
).
9.3.4
Buffer Length register (address: 1Ch)
This register determines the current packet size (DATACOUNT) of the indexed
endpoint FIFO. The bit allocation is given in
Table 37
.
The Buffer Length register is automatically loaded with the FIFO size, when the
Endpoint MaxPacketSize register is written (see
Table 41
). A smaller value can be
written when required. After a bus reset, the Buffer Length register is made zero.
IN endpoint:
When data transfer is performed in multiples of MaxPacketSize, the
Buffer Length register is not significant. This register is useful only when transferring
data that is not a multiple of MaxPacketSize. The following two examples
demonstrate the significance of the Buffer Length register.
Table 35:
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Data Port register: bit allocation
15
14
13
12
DATAPORT[15:8]
0
0
R/W
4
DATAPORT[7:0]
0
0
R/W
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 36:
Bit
15 to 8
7 to 0
Data Port register: bit description
Symbol
DATAPORT[15:8]
DATAPORT[7:0]
Description
data (upper byte)
data (lower byte)
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