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參數資料
型號: ISP1760BE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus host controller for embedded applications
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-425-1, LQFP-128
文件頁數: 35/105頁
文件大?。?/td> 449K
代理商: ISP1760BE
9397 750 13257
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 — 8 November 2004
35 of 105
Philips Semiconductors
ISP1760
Embedded Hi-Speed USB host controller
[1]
The reserved bits should always be written with the reset value.
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal
Serial Bus Rev. 1.0
8.2.7
PORTSC1 register (R/W: 0064h)
The Port Status and Control (PORTSC) register (bit allocation:
Table 22
) is in the power
well. It is reset by hardware only when the auxiliary power is initially applied or in response
to a Host Controller reset. The initial conditions of a port are:
No peripheral connected
Port disabled.
If the port has power control, software cannot change the state of the port until it sets the
port power bits. Software must not attempt to change the state of the port until the power
is stable on the port (maximum delay is 20 ms from the transition).
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
23
22
21
20
19
18
17
16
reserved
[1]
0
0
0
0
0
0
0
0
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
reserved
[1]
0
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
CF
0
R/W
reserved
[1]
0
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Table 21:
Bit
31 to 1
0
CONFIGFLAG register: bit description
Symbol Description
[1]
-
reserved
CF
Configure Flag
: The host software sets this bit as the last action when it is
configuring the Host Controller. This bit controls the default port-routing
control logic.
Table 22:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
PORTSC1 register: bit allocation
31
30
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
reserved
[1]
PTC[3:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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