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參數資料
| 型號： | ISPLSI5512VA-70LB388I |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復雜可編程邏輯器件 |
| 文件頁數： | 10/12頁 |
| 文件大小： | 120K |
| 代理商： | ISPLSI5512VA-70LB388I |
Specifications
ispLSI 1048
10
device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
COMMERCAL&INDUSTRAL
74
DESGNS
Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
Pin Description
Input
–
Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK options become active.
Input
–
This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as an input
pin to load programming data into the device. SDI/IN 0 also is used as
one of the two control pins for the isp state machine.
Input
–
This pin performs two functions. It is a dedicated input pin when
ispEN is logic high. When ispEN is logic low, it functions as a pin to
control the operation of the isp state machine.
Input/Output
–
This pin performs two functions. It is a dedicated input
pin when ispEN is logic high. When ispEN is logic low, it functions as
an output pin to read serial shift register data.
Input
–
This pin performs two functions. It is a dedicated input when
ispEN is logic high. When ispEN is logic low, it functions as a clock pin
for the Serial Shift Register.
Ground (GND)
V
CC
GND
V
CC
46, 76,106, 16
15, 45, 77, 107
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
20, 21, 22, 23, 24, 25,
26, 27, 28, 29, 30, 31,
32, 33, 34, 35, 36, 37,
38, 39, 40, 41, 42, 43,
49, 50, 51, 52, 53, 54,
55, 56, 57, 58, 59, 60,
61, 62, 63, 64, 65, 66,
67, 68, 69, 70, 71, 72,
80, 81, 82, 83, 84, 85,
86, 87, 88, 89, 90, 91,
92, 93, 94, 95, 96, 97,
98, 99,100,101,102,103,
109,110,111,112,113,114,
115,116,117,118,119,120,
1,
2,
3,
7,
8,
9, 10, 11, 12
4
5,
6,
IN 4
IN 6 - IN 11
48,
79,104,105,
–
108, 13
Dedicated input pins to the device. (IN 2 and IN 9 not available)
RESET
18
Y0
14
Y1
78
Y2
75
Y3
Table 2- 0002C-48-isp
DESCRIPTION
NAME
PQFP PIN NUMBERS
ispEN
17
SDI/IN 0
1
19
MODE/IN 1
1
44
SDO/IN 3
1
47
SCLK/IN 5
1
73
1. Pins have dual function capability.
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| ISPLSI5512VE-100LB388 | |
| ISPLSI5512VE-100LB388I | Electrically-Erasable Complex PLD |
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相關代理商/技術參數 |
參數描述 |
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| ISPLSI5512VA-70LQ208 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-770LB272 | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI5512VE-100LB272 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-100LB272I | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VE-100LB388 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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