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參數(shù)資料
| 型號(hào)： | ISPLSI8840-110LB432 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類(lèi)： | PLD |
| 英文描述： | In-System Programmable SuperBIG⑩ High Density PLD |
| 中文描述： | EE PLD, 13.5 ns, PBGA432 |
| 封裝： | BGA-432 |
| 文件頁(yè)數(shù)： | 1/23頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | ISPLSI8840-110LB432 |
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ispLSI
In-System Programmable
SuperBIG High Density PLD
8840
8840_07
1
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Features
SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 5V Power Supply
— 45,000 PLD Gates/840 Macrocells
— Up to 312 I/O Pins Supporting 3.3V/5V I/O
— 1152 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
HIGH-PERFORMANCE E
2
CMOS
TECHNOLOGY
—
f
max
= 110 MHz Maximum Operating Frequency
—
t
pd
= 8.5 ns Propagation Delay
— TTL Compatible Inputs and 3.3V/5V Outputs
— PCI Compatible Inputs, Outputs and Speed Grades
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
5V IN-SYSTEM PROGRAMMABLE
ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply for Output Drivers
Supports 5V or 3.3V Outputs
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
ispDesignEXPERT – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
Functional Block Diagram
ispLSI 8000 Family Description
The ispLSI 8000 Family of Register-Intensive, SuperBIG
In-System Programmable Logic Devices is based on Big
Fast Megablocks of 120 registered macrocells and a
Global Routing Plane (GRP) structure interconnecting
the Big Fast Megablocks. Each Big Fast Megablock
contains 120 registered macrocells arranged in six groups
of 20, a group of 20 being referred to as a Generic Logic
Block, or GLB. Within the Big Fast Megablock, a Big Fast
Megablock Routing Pool (BRP) interconnects the six
GLBs to each other and to 24 Big Fast Megablock I/O
Global Routing Plane
12
I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
Big Fast Megablock 4
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
Big Fast Megablock 2
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
12
I/O
Boundary
Scan
8840 block
January 2000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI8840-60LB432 | In-System Programmable SuperBIG⑩ High Density PLD |
| ISPLSI8840-90LB432 | In-System Programmable SuperBIG⑩ High Density PLD |
| ISPMACH4ACPLDFAMILY | High Performance E 2 CMOS In-System Programmable Logic |
| ISPPAC-CLK5520V-01TN100C | Linear Array Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:530nm |
| ISPPAC-CLK55xx | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI8840-60LB432 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 5000MV HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI8840-90LB432 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 5000MV HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI-8840V-125LB272 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ispLSI8840V-125LB272 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 5000MV RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI8840V-125LB492 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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