
ispPAC 20
In-System Programmable Analog Circuit
pac20_05
1
Copyright 2001 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
May 2001
Typical Application Diagram
Functional Block Diagram
Features
IN-SYSTEM PROGRAMMABLE (ISP) ANALOG
— Two Instrument Amplifier Gain/Attenuation Stages
— Signal Summation (Up to 3 Inputs)
— Precision Active Filtering (10kHz to 100kHz)
— 8-Bit DAC and Fast Dual Comparator
— Non-Volatile E
2
CMOS
Cells (10,000 Cycles)
— IEEE 1149.1 JTAG Serial Port Programming
LINEAR ELEMENT BUILDING BLOCKS
— Programmable Gain Range (0dB to 40dB)
— Bandwidth of 550kHz (G=1), 330kHz (G=10)
— Low Distortion (THD < -74dB max @ 10kHz)
— Auto-Calibrated Input Offset Voltage
TRUE DIFFERENTIAL I/O
— High CMR (69dB) Instrument Amplifier Inputs
— 2.5V Common Mode Reference on Chip
— Rail-to-Rail Voltage Outputs
— Single Supply 5V Operation
44-PIN PLASTIC PLCC AND TQFP PACKAGES
APPLICATIONS INCLUDE INTEGRATED:
— Single +5V Supply Signal Conditioning
— Active Filters, Gain Stages, Summing Blocks
— Analog Front Ends, 12-Bit Data Acq. Systems
— Precision Voltage Controlled Oscillator
— Synchronous Detection Circuits
— Precision Rectification & Other Non-Linear Functions
Description
The ispPAC20 is a member of the Lattice family of In-
System Programmable analog circuits, digitally configured
via nonvolatile E
2
CMOS technology.
Analog building blocks, called PACblocks, replace tradi-
tional analog components such as opamps and active
filters, eliminating the need for most external resistors and
capacitors. Also included are an 8-bit DAC and dual com-
parators. With no requirement for external configuration
components, ispPAC20 expedites the design process,
simplifying prototype circuit implementation and change,
while providing high-performance integrated functionality.
Designers configure the ispPAC20 and verify its perfor-
mance using PAC-Designer
, an easy-to-use, Microsoft
Windows
compatible program. Device programming is
supported using PC parallel port I/O operations.
The ispPAC20 is configured through its IEEE Standard
1149.1 (JTAG) compliant serial port. The flexible In-System
Programming capability enables programming, verification
and reconfiguration if desired, directly on the printed circuit
board.
Vin
Ref+
Ref-
Ain-
Ain+
12-Bit
Differential
Input ADC
DAC
ispPAC20
5V
5V
DAC
CP1OUT
OUT1
IA
OA
OA
CP
CP
IA
IA
IA
OUT2
CP2OUT
3VREF
1.5VREF
Window
IN1
GND
MSEL
VCC
P
J
D
V
DACOUT
IN2
C
E
D
C
C
IN3
CPIN
Logic
Logic
E
2
CMOS Mem
Auto-Cal
Reference
ISP Control
Analog Routing Pool