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參數資料
| 型號： | K3S7V2000M-TC30 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM |
| 中文描述： | 6400位（4Mx16 / 2Mx32）同步MASKROM |
| 文件頁數： | 1/27頁 |
| 文件大小： | 1080K |
| 代理商： | K3S7V2000M-TC30 |
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K3S7V2000M-TC
64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
Synch. MROM
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Address: Row address: RA
0
~ RA
12
Column address: CA
0
~ CA
7
(x32): CA
0
~ CA
8
(x16)
Switchable organization
4,194,304 x 16(word mode) /
2,097,152 x 32(double word mode)
All inputs are sampled at the rising edge of the system clock
Read Performance at memory point of view
@33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3)
@50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
@66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
@83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
@100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
t
SAC
: 6ns
Default mode by user requirement
MRS cycle with address key programs
-. RAS Latency(1 & 2)
-. CAS Latency(3 ~ 6)
-. Burst Length : 4, 8
-. Burst Type : Sequential & Interleaved
DQM for data-out masking
Package :86TSOP2 - 400
GENERAL DESCRIPTION
The K3S7V2000M-TC is a synchronous high bandwidth mask
programmable ROM fabricated with SAMSUNG
′
s high perfor-
mance CMOS process technology and is organized either as
4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double
word mode) depending on polarity of WORD pin.(see pin func-
tion description). Synchronous design allows precise cycle con-
trol, with the use of system clock, I/O transactions are possible
on every clock cycle. Range of operating frequencies, program-
mable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
FEATURES
ORDERING INFORMATION
Part NO.
MAX Freq.
Interface
Package
K3S7V2000M-TC10
100MHz
LVTTL
86TSOP2
K3S7V2000M-TC12
83MHz
K3S7V2000M-TC15
66MHz
K3S7V2000M-TC20
50MHz
K3S7V2000M-TC30
33MHz
FUNCTIONAL BLOCK DIAGRAM
*
Samsung Electronics reserves the right to
change products or specification without notice.
Timing Register
4M x 16 /2M x 32
S
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
C
L
LCKE
LRAS
LMR
CLK
CKE
MR
RAS
CAS
CS
CLK
ADD
LCAS
Output Buffer
. . .
Q0
Q16
Q15
Q31
Cell Array
DQM
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