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參數(shù)資料
| 型號： | L64014A |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 196K |
| 代理商： | L64014A |
10
L64014 PCMCIA Bridge
DS_N
Decoder Data Strobe
Output
The L64014 asserts this signal LOW to strobe data in or
out of the L64020 DVD Decoder.
HS_N
Decoder Horizontal Sync
Output
HS_N is the horizontal sync signal to the DVD Decoder
and NTSC/PAL Encoder. HS_N is synchronous to
CLK27.
IRQ_N
Decoder Interrupt Request
Input
The L64020 asserts this signal LOW to tell the L64014
that an unmasked interrupt condition has occurred in the
DVD Decoder.
LRCLK
Decoder Audio Left/Right Clock
Input
Using the default setting, LRCLK is driven HIGH when
the ASDATA pin has a right channel sample, and LRCLK
is driven LOW when the ASDATA pin has a left channel
sample.
PD[7:0]
Decoder Pixel Data[7:0]
Input
The PD[7:0] bus carries the pixel data for the recon-
structed pictures. The pixel data is formatted in ITU_R
BT.601 YCbCr chromaticity.
RD/WR_N
Decoder Read/Write
Output
The L64014 drives this signal HIGH for a read cycle or
drives it LOW for a write cycle. The L64014 also asserts
the chip select signal (CS_N) during a write or read cycle.
RST_N
Decoder Reset
Output
When the L64014 asserts RST_N, the L64020 resets its
internal microcontroller, FIFO controllers, state machines,
and registers. The minimum reset pulse width is 8 CLK27
cycles (SYSCLK). Both CLK27 and ACLK must be
running during reset.
VREQ_N
Decoder Video Request
Input
The DVD Decoder asserts VREQ_N when it is ready to
receive a new byte of coded audio data in A/V PES
stream mode. The decoder is ready when the channel
FIFO is not near full. VREQ_N is not used in program
stream modes.
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