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參數資料
| 型號： | L64724QC |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 3/32頁 |
| 文件大小： | 338K |
| 代理商： | L64724QC |
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L64724 Satellite Receiver
11
D[7:0]
Data
Bidirectional
The D[7:0] signals form the bidirectional data bus, which
is the input data bus when data is written to the L64724
chip and the data output bus when the L64724 chip is
read in Parallel Host Interface mode (the HOST_MODE
pin is HIGH). The data lines are 3-stated when not being
read or written. When Serial Host Interface mode is
selected (the HOST_MODE pin is LOW), D[0] is used as
the Serial Clock (SCLK) signal to synchronize the transfer
of serial data on the Serial Data (SDATA) pin
(XCTR_OUT[1] functions as SDATA), D[1] is used as the
SDATA signal to transfer of serial data, and D[2] and D[3]
are used as the two LSBs of the L64724 slave address.
DTACK/POL
Data Acknowledge/Wait Polarity
Input
The DTACK/POL signal determines the polarity of the
Data Acknowledge/Wait Signal. When the DTACK/POL
signal is LOW, DTACK/WAIT is active-LOW. When
DTACK/POL is HIGH, DTACK/WAIT is active-HIGH.
DTACK/WAIT Data Acknowledge/Wait
Output
The DTACK/WAIT signal is an output indicating that the
transaction on the D[7:0] bus has been completed. It is
active-LOW when DTACK/POL is LOW and active-HIGH
when DTACK/POL is HIGH.
HOST_MODE
Serial or Parallel Host Interface Select
Input
When the HOST_MODE signal is deasserted, it selects
the Serial Host Interface mode. When it is asserted, it
selects the Parallel Host Interface mode.
INT
Interrupt
Output
The L64724 asserts the INT signal (LOW) when an inter-
nal unmasked interrupt ag is set. The INT signal
remains asserted as long as the interrupt condition per-
sists and the interrupt ag is not masked.
READ/WRITE Read/Write Strobe
Input
The microcontroller asserts the READ/WRITE signal
(HIGH) to indicate that the current transaction is a read
from the L64724, and deasserts it (LOW) to indicate that
it is a write to the L64724.
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