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參數(shù)資料
型號: L64724QC
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 31/32頁
文件大小: 338K
代理商: L64724QC
8
L64724 Satellite Receiver
DVALIDOUT
Valid Data Out
Output
The DVALIDOUT signal indicates that the CO[7:0] signals
contain the corrected channel data. New data is valid on
the output when the DVALIDOUT signal is asserted.
DVALIDOUT is not asserted during the propagated check
and GAP bytes. The DVALIDOUT signal is deasserted
after the FEC_RST register bit (Group 4, APR 55) is set
to a one.
ERROROUT
Error Detection Flag
Output
The L64724 asserts the ERROROUT pin to ag uncor-
rectable errors. The L64724 asserts the ERROROUT sig-
nal at the beginning of any frame that contains an
uncorrectable error, and deasserts it at the end of the
frame if the error condition is removed. ERROROUT is
exactly aligned with the output data stream.The
ERROROUT signal is asserted after the FEC_RST
register bit (Group 4, APR 55) is set to a one.
FSTARTOUT
Frame Start Output
Output
The L64724 asserts the FSTARTOUT signal during the
rst bit of every frame with valid data in Serial Channel
Output mode and during the rst byte in Parallel Channel
Output mode. FSTARTOUT is valid only when the
DVALIDOUT signal is asserted. The FSTARTOUT signal
is deasserted after the FEC_RST register bit (Group 4,
APR 55) is set to a one.
PLL Interface
The PLL circuitry multiplies the Channel Clock Recovery circuit Serial
Clock (SCLK) signal (XCTR_OUT[0] functions as SCLK) by 2, 3, or 4
times the symbol rate, based on the Viterbi code rate.
LCLK
Decimated Clock Output
Output
The L64724’s internal clock generation module generates
the LCLK signal. LCLK is derived from CLK by dividing
by the value of the CLK_DIV2 parameter.
LP2
Input to VCO
Input
The LP2 signal is the input to the internal voltage-
controlled oscillator. It is normally connected to the output
of an external RC timing circuit.
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相關代理商/技術參數(shù)
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