- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄30713 > L64733C-48 (LSI CORP) SPECIALTY CONSUMER CIRCUIT, PQFP48 PDF資料下載
參數(shù)資料
| 型號： | L64733C-48 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 4/52頁 |
| 文件大小： | 552K |
| 代理商： | L64733C-48 |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
12
L64733C/L64734 Tuner and Satellite Receiver Chipset
FDOUB
Frequency Doubler
Input
When FDOUB is asserted, the L64733C local oscillator
frequency is internally doubled and fed to the mixers.
When FDOUB is deasserted, the oscillator frequency is
not doubled before being fed to the mixers.
Bit 6 of register 79, group 4 (APR 79), controls the
L64734 FDOUB output pin, which enables or disables the
frequency doubler on the L64733C.
The FDOUB pin is set as shown in the table below, where
Fswitch is the frequency at which the frequency doubler is
enabled or disabled.
This method of control preserves the compatibility with
the L64733B, which is not affected by 3-stating the
FDOUB pin.
FLCLK
Filter Clock
Input
The FLCLK signal is a low amplitude, self-biased clock
input. The frequency of the FLCLK signal multiplied by 16
is the baseband lter’s
3 dB frequency.
IDCp, IDCn
I-Channel DC Offset Correction
Input
Connect a 0.1
F or larger capacitor between the IDCp
and IDCn signals.
INSEL
RF Port Input Select
Input
When the INSEL signal is asserted, the L64733C is in
normal mode. When the INSEL signal is deasserted, the
L64733C is in Loop-Through mode. In this mode, the
RFIN signal is looped through out to the RFOUT signal
and the L64733C local oscillator is shut off.
LOBUF
Local Oscillator Buffer Select
Input
Asserting LOBUF causes the external PLL mode to be in
effect, the local oscillator (LO) buffer to be enabled, and
the LO signal to be sent out to the PSOUT pins according
to the division ratio selected with the LODIV signal. When
Frequency
FDOUB
APR 79[6]
TRI
APR 79[2]
FDOUB
Pin
925 MHz–Fswitch
0
LOW
Fswitch–1680 MHz
1
3-state
1680–2175 MHz
1
0
HIGH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L64781 | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| L6561 | 0.7 A POWER FACTOR CONTROLLER, PDIP8 |
| L6566ATR | 0.8 A POWER FACTOR CONTROLLER WITH POST REGULATOR, 300 kHz SWITCHING FREQ-MAX, PDSO16 |
| L6605D | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| L6605 | SPECIALTY CONSUMER CIRCUIT, PDIP18 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L64734 | 制造商:LSI 制造商全稱:LSI 功能描述:Tuner and Satellite Receiver Chipset |
| L64734C-45 | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| L64735GM-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735GM-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735GM-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。