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參數資料
型號: L9824
文件頁數: 4/11頁
文件大小: 229K
代理商: L9824
ELECTRICAL CHARACTERISTICS
(continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
n
ON
ON-delay Time (5)
See fig. 1
R
L
= 1K
10
ms
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
t
n
OFF (3)
t
s
ON
OFF-delay Time (5)
10
ON-delay Time (6)
20
100
t
s
OFF (3)
OFF-delay Time (6)
20
40
t
D
ON
t
D
OFF (3)
Data ON - Delay Time (7)
2
10
Data OFF - Delay Time (7)
2
10
t
ON
-t
OFF
t
f
Delay Time Difference
Except STANDBY MODE
4
Filter Time (8)
0.7
2
4
Notes :
2. If the output current exceeds thehigh short current threshold I
SC
an internal timeris started. If afterthetime period of T
TSC
the current
limitingis still active the overload condition is recognized andthis output is switchedoff. To restart the output theTRANSFER MODE
has to be chosen and the corresponding input voltage V
DIN
must become HIGH to reset the internal overload latch.
3. Becausethe output capacitance is the drain-source capacitance of the power switch the risetime ofthe outputs depends of the used
supply voltageV
S
, the load resistor R
L
and the output capacitance C
OUT
andcan be calculated with the followingequation :
T
d
=
τ
In10 (reaching 90% of V
S
)
τ
=R
L
xC
OUT
xK (4) K = 1.5
This additional delay time T
must be addedto t
.
4. Becausethe drain source capacitance of the output transistor is voltage dependent, it is necessary to multiply C
OUT
(specified at the
maximum V
OUT
) with a correction factor K to obtain the average output capacitance C
OUT
.
5. Delay timebetween all modes except STANDBYMODE.
6. Delay timebetween STANDBY MODE and any other mode and vice versa.
7. Data delay time when TRANSFER MODE is chosen.
8. Explanation see page 6.
MODE CHANGE DIAGRAM
.
Critical mode variations occur when both mode
inputschange their statesimultaneously.This is
representedby the diagonalarrows in the mode
changediagram.
FILTERING TIMING
.
To avoidthata filter is implementedin the TM si-
gnal path.A suitable filter time t
f
is chosen to be
well beyondthe mode comparatordelays.
L9824
4/11
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