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參數資料
| 型號： | LC0710LG |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA40 |
| 封裝： | 4.40 X 3.60 MM, FLGA-40 |
| 文件頁數： | 16/22頁 |
| 文件大小： | 426K |
| 代理商： | LC0710LG |
LC72713W
No.6870-3/29
Allowable Operating Ranges: Parallel Interface at Ta=-40 to +85°C, VSS=0V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
[Parallel I/O]
Address to RD setup
tSARD
A0/CL, A1/CE, A2/DI, A3, RD
20
nS
RD to address hold
tHARD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250ns
-20
nS
RD low-level width
tWRDL1
RD
250
nS
RD low-level width (when RDY is used)
tWRDL2
RD
100
nS
RD cycle wait
tCYRD
A0/CL, A1/CE, A2/DI, A3, RD
150
nS
RDY width (Register read)
tWRDY
RDY
60
210
nS
RD data hold
tRDH
RD, DATn
0
nS
Address to WR setup
tSAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
nS
WR to address hold
tHAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
nS
WR cycle wait
tCYWR
A0/CL, A1/CE, A2/DI, A3, WR
150
nS
WR low-level width
tWWRL
WR
200
nS
WR data hold
tWDH
WR, DATn
0
nS
RDY output delay
tDRDY
RD, RDY
0
30
nS
Corrected output RD width
tWDRD1
RD (BUSWD=L 8bits)
300
nS
RD (BUSWD=H 16bits)
540
nS
Corrected output RD width
tWDRD2
RD (BUSWD=L 8bits)
100
nS
(when RDY is used)
RD (BUSWD=H 16bits)
300
nS
RDY width (corrected output read)
tWDRDY
RDY (BUSWD=L 8bits)
60
210
nS
RDY ((BUSWD=H 16bits)
300
490
nS
DACK to DREQ delay
tDREQ
DREQ, DACK
260
nS
DMA cycle wait
tCYDM
RD, DREQ
420
nS
RD low-level width (DMA)
tWRDM
RD
300
nS
Notes: Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 250ns (minimum).
Electrical Characteristics at VDD=+4.5 to +5.5V, within the allowable operating ranges
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
VOH1
IO=2mA, BCK, FCK, BLOCK, FLOCK,
VDD-0.4
V
High-level output voltage
CRC4, CLK16, DATA
VOH2IO=4mA, INT, RDY, DREQ, D0 to D15
VDD-0.4
V
VOL1IO=2mA, Pins for which VOH1 applies
0.4
V
Low-level output voltage
VOL2IO=4mA, Pins for which VOH2 applies
0.4
V
VOL3IO=2mA, DO, INT
0.4
V
IIH1
VIN=5.5V, A0/CL, A1/CE, A2/DI, RST,
1.0
μA
High-level input current
STNBY
IIH2VIN=VDDD, All input pins other than IIH1
1.0
μA
Low-level input current
IIL
VIN=VSSD, All input pins
-1.0
μA
Input resistance
RMPX
MPXIN -Vssa f=100kHz
50
kΩ
Reference supply voltage output
Vref
Vref, Vdda=5V
2.5
V
Bandpass filter center frequency
Fc
FLOUT
76.0
kHz
-3 dB bandwidth
Fbw
FLOUT
19.0
kHz
Group delay
Dgd
FLOUT
-7.5
+7.5
μs
Gain
FLOUT-MPXIN, f=76kHz
20
dB
ATT1
FLOUT, f=50kHz
25
dB
Stop band attenuation
ATT2
FLOUT, f=100kHz
15
dB
ATT3
FLOUT, f=30kHz
50
dB
ATT4
FLOUT, f=150kHz
50
dB
Output off leakage current
IOFF
VO=VDDD, DO
5.0
μA
Hysteresis voltage
VHYS
A0/CL, A1/CE, A2/DI, A3, CS, RD, WR,
0.1VDDDV
DACK, IOCNT1, IOCNT2, RST, STNBY
Internal feedback resistor
Rf
XIN, XOUT
1.0
MΩ
Current drain
IDD
18
25
mA
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