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參數資料
| 型號： | LC07410LG |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA40 |
| 封裝： | 4.40 X 3.60 MM, FLGA-40 |
| 文件頁數： | 18/36頁 |
| 文件大小： | 367K |
| 代理商： | LC07410LG |
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LC07410LG
No.A1345-25/36
BPHZ[2:0]
fsig
BPTON[2:0]
Ton
BPTOFF[4:0]
Toff
BPTOFF[4:0]
Toff
000
1kHz
000
20ms
00000
0ms
01011
210ms
001
2kHz
001
40ms
00001
10ms
01100
230ms
010
3kHz
010
60ms
00010
30ms
01101
250ms
011
4kHz
011
80ms
00011
50ms
01110
270ms
100
5kHz
100
100ms
00100
70ms
01111
290ms
101
6kHz
101
120ms
00101
90ms
10000
310ms
110
7kHz
110
140ms
00110
110ms
10001
330ms
111
8kHz
111
160ms
00111
130ms
10010
350ms
01000
150ms
10011
370ms
01001
170ms
10100
390ms
01010
190ms
BPCNT[3:0]
Nrep
BPCNT[3:0]
Nrep
0000
infinite
1000
8
0001
1
1001
9
0010
2
1010
10
0011
3
1011
11
0100
4
1100
12
0101
5
1101
13
0110
6
1110
14
0111
7
1111
15
PLL
(a) PLL mode (PLL_PDX = 1)
In this mode, the 256fs clock (MCLK) used by the CODEC block is generated from the clock (12, 13.5, 24 and
27MHz frequencies supported) which is input from MCLKIN, and BCLK and LRCK are output.
Sampling frequencies (fs) of 7.86kHz to 48kHz are supported.
fs setting
fs is set by setting the division ratio for each of the three frequency dividers (DIV1, DIV2, and DIV3) in respective
registers.
1. Set FCKI[2:0] for the MCLKIN frequency, results in 12MHz or 13.5MHz as the frequency input to DIV1.
2. Set DIV1, DIV2, and DIV3, while referring to the division ratio setting example table.
ex. "FCKI = 2, DIV1 = 125, DIV2 = 128, DIV3 = 2" in case of "MCLKIN = 24MHz, fs = 24kHz"
(b) EXT mode (PLL_PDX = 0)
In this mode, the 256fs clock (MCLK) from MCLKIN is input and used.
When ADF_MASTER is 1, BCLK and LRCK whose frequency is obtained by dividing the frequency of MCLKIN
are output.
When ADF_MASTER is 0, BLCK and LRCK are external inputs.
* In the CODEC block, BCLK and LRCK must be synchronized with MCLK.
In PLL mode (PLL_PDX = 1), operation must be performed in BCLK output mode (ADF_MASTER = 1). In EXT
mode (PLL_PDX = 0) and when ADF_MASTER is 0, BCLK and LRCK synchronized with MCLK must be input.
256fs
DIV3
DIV1
FCKI
DIV2
MCLKIN
f
MCKOUT
f
=
×
=
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