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參數資料
| 型號： | LC3564BM-10 |
| 文件頁數： | 9/9頁 |
| 文件大?。?/td> | 145K |
| 代理商： | LC3564BM-10 |
PS No. 5804-9/9
LC3564B, BS, BM, BT-70/10
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
I
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
I
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
I
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Data retention supply voltage
V
DR
V
CE2
≤
0.2 V or
V
CE1
≥
V
CC
– 0.2 V, V
CE2
≥
V
CC
– 0.2 V
V
CC
= 3V, V
CE2
≤
0.2 V,
or V
CE1
≥
V
CC
– 0.2 V,
V
CE2
≥
V
CC
– 0.2 V
2.0
5.5
μA
Ta
≤
70°C
0.8
μA
Data retention supply current
I
CCDR
Ta
≤
85°C
2.5
Chip enable setup time
t
CDR
t
R
0
ns
Chip enable hold time
t
RC
*
ns
Data Retention Characteristics
at Ta = –40 to +85°C
Note
*
: t
RC
is the read cycle time.
Note
*
:In 5-V operation: 4.5 V
In 3-V operation: 2.7 V
Data retention mode
Data Retention Waveforms (1): CE1 Control
Notes on Circuit Design
When actually design a circuit using these devices, take the following points into consideration and design the circuit so
that none of the maximum rating items are ever exceeded.
Variations in the supply voltage
Variations in the electrical characteristics of components such as semiconductor devices, resistors, and capacitors.
Ambient temperature
Variations in input and clock signals
Possible application of abnormal pulses
Also, these devices must be operated within the ranges stipulated in the allowable operating ranges.
If CMOS IC input pins are left open, intermediate potential input voltages may occur leading to incorrect operation due
to through currents or other phenomenon. Applications must handle unused input pins appropriately.
Data Retention Waveforms (2): CE2 Control
Data retention mode
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PDF描述 |
|---|---|
| LC3564CT-70U | |
| LC3564P_SERIES | |
| LC3564PL-10 | |
| LC3564PL-12 | |
| LC3564PL-12L | |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LC3564BM-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LC3564BS | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:64K (8192-word ⅴ 8-bit) SRAM with OE, CE1, and CE2 Control Pins |
| LC3564BS-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC3564BS-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LC3564BT | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:64K (8192-word ⅴ 8-bit) SRAM with OE, CE1, and CE2 Control Pins |
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