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參數(shù)資料
型號(hào): LC4384B-75F256C
文件頁(yè)數(shù): 20/57頁(yè)
文件大小: 1078K
代理商: LC4384B-75F256C
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
20
Timing Model
The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing
model provided in Figure 10 shows the speci
fi
c delay paths. Once the implementation of a given function is deter-
mined either conceptually or from the software report
fi
le, the delay path of the function can easily be determined
from the timing model. The Lattice design tools report the timing delays based on the same timing model for a par-
ticular design. Note that the internal timing parameters are given for reference only, and are not tested. The exter-
nal timing parameters are tested and guaranteed for every device. For more information on the timing model and
usage, please refer to Technical Note TN1004:
ispMACH 4000 Timing Model Design and Usage Guidelines.
Figure 10. ispMACH 4000 Timing Model
DATA
MC Reg.
C.E.
S/R
Q
SCLK
IN
OE
In/Out
Delays
In/Out
Delays
Control
Delays
Register/Latch
Delays
Routing/GLB Delays
Out
Note: Italicized items are optional delay adders.
t
FBK
Feedback
From
Feedback
t
BUF
t
IOO
t
EN
t
DIS
t
PDb
t
MCELL
t
EXP
t
PTCLK
t
BCLK
t
PTSR
t
BSR
t
GPTOE
t
PTOE
t
ROUTE
t
BLA
t
INREG
t
INDIO
t
IN
t
IOI
t
GCLK_IN
t
IOI
t
GOE
t
IOI
t
PDi
t
ORP
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LC4384B-75F256I1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4384B-75FN256C 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4384B-75FN256C1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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