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參數資料
| 型號： | LC7073 |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP18 |
| 封裝： | DIP-18 |
| 文件頁數： | 8/9頁 |
| 文件大小： | 141K |
| 代理商： | LC7073 |
LC7073, 7073M
No.3932–8/9
Figure 8. Reset input
Figure 9. Supply rise time vs. reset delay
A minimum delay of 10 ms should be allowed for oscillator stabilization. A 10 to 100 ms reset delay is generated using
a 0.1
F reset capacitor, C. A larger capacitor should be used if the supply rise time is longer.
Figure 10. System block diagram
Device Comparison
The LC7070N, LC7070M and LC7071NM have identical basic functions, pinouts and input/output timing to those of the
LC7073 and LC7073M. Their respective packages and output circuitry are compared in table 3.
Table 3. Device comparison
The differences in output data format between the LC7070N/LC7070NM/LC7071NM and LC7073/LC7073M are as
follows.
Offset Words E and F
The LC7070N/LC7070NM/LC7071NM recognizes offset words E and F and performs group sync detection. The LC7073/
LC7073M does not recognize offset words E and F–it only detects A, B, C, C’ and D.
Input Data Bits
If all data bits are 0, the LC7070N/LC7070NM/LC7071NM only recognizes offset word E. The LC7073/LC7073M does
not recognize the offset word E block. No sync detection occurs if all input data bits are 0. Once data cutoff has been
determined, output data stops and the sync cutoff sequence begins.
e
c
i
v
e
De
g
a
k
c
a
Pe
p
y
t
u
p
t
u
O
N
0
7
0
7
C
LP
I
D
n
i
p
-
8
1
n
i
a
r
d
-
n
e
p
O
M
N
0
7
0
7
C
LP
F
M
n
i
p
-
8
1
M
N
1
7
0
7
C
LP
F
M
n
i
p
-
8
1
s
r
o
t
s
i
s
n
a
r
t
S
O
M
g
n
i
s
u
e
l
o
p
-
m
e
t
o
T
3
7
0
7
C
LP
I
D
n
i
p
-
8
1
M
3
7
0
7
C
LP
F
M
n
i
p
-
8
1
VDD
RES
C=0.1
F
Start point
0.8VDD
VDD
4.5V
1.125V
(0.25VDDmin)
RES
Oscillator stabilization
time (10 to 100 ms)
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相關代理商/技術參數 |
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| LC7074M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Synchronous Error Correction LSI for RDS Applications |
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