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參數(shù)資料
| 型號(hào)： | LC72711W |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁(yè)數(shù)： | 13/26頁(yè) |
| 文件大小： | 157K |
| 代理商： | LC72711W |
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LC72711W, 72711LW
No.6167-20/26
CPU Connection Example <Parallel Interface>
This section presents examples of the connection of this IC to a CPU.
Note that care is required with respect to read timing, since the time required to read a register, and the time required
to read a post-correction data packet (22 bytes) are different.
Normal connection
When hardware waits are applied to the
CPU, the wait time (RDY width)
requires care.
BUSWD = low: 8 bits
BUSWD = high: 16 bits
DMA transfer mode
I/O read/write operations are used for the
normal register read and write operations.
However, programmable wait states may need
to be inserted, depending on the execution
speeds. DMA processing is only used for
readout of post-correction data.
Applications can select whether RD or DACK
is used as the DMA read control signal by
setting a register.
The default is to use the RD signal.
The data bus width in DMA mode is
always 8 bits.
CPU DMA mode setting example
(For reference only)
SH Series: Transfer type: 2-cycle
transfer
Transfer mode: Single
transfer mode
V Series: Address mode: Dual
address mode
Bus mode: Cycle
stealing mode
The source side (the FM multiplex IC)
address is fixed at 0.
RST
IOCNT2
IOCNT1
WAIT
INT
CS
RD
WR
RD
CS
INT
RDY
DACK
DREQ
SP
RST
IOCNT2
DREQ
INT
CS
RD
WR
RD
CS
INT
RDY
SP
LC72711W,
LC72711LW
LC72711W,
LC72711LW
D0 to D7
(D0 to D15)
A0 to A3
BUSWD
BUS-Width
8bits
PORT1
CPU
PORT1
DACK
DREQ
DACK
BUS-Width
8bits
CPU
D0 to D7
A0 to A3
BUSWD
IOCNT1
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