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參數資料
| 型號： | LC72713W |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 20/22頁 |
| 文件大小： | 201K |
| 代理商： | LC72713W |
LC72713W
No.6870-7/29
Continued from preceding page.
Address
Register
Function
R/W
Address
Register
Function
R/W
1
BIC
Number of allowable BIC errors
W
1
STAT
Status register
R
2
SYNCB
Block synchronization: error protection count
W
2
BLNO
Block number register
R
3
SYNCF
Frame synchronization: error protection count
W
4
CTL1
Control register 1
W
5
CTL2
Control register 2
W
6
CRC4
Layer 4 CRC register
W
Number of Allowable BIC Errors
Address
Register
R/W
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
01H
BIC
W
22H
Back protection
(LSB)
Forward protection
(LSB)
The synchronization circuit in this IC operates by recognizing a 16-bit BIC code. The number of allowable errors is the
number of incorrect bits allowed in those 16 bits. This data sets up separate values for forward protection mode (when
synchronized) and for back protection mode (when not synchronized).
The default value is to allow 2 incorrect bits in both forward and back modes. If the block synchronization
discrimination output (BLOCK) is used for discriminating whether or not FM multiplex data is present, we recommend
setting the back protection mode BIC allowable error count to 1 or 0.
Block Synchronization: Error Protection Count
Address
Register
R/W
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
02H
SYNCB
W
17H
Back protection
(LSB)
Forward protection
(LSB)
The synchronization protection count can be set separately for both forward and back protection. The count conditions
for the protection counts are as follows.
Back protection mode (not synchronized: BLOCK=low)
If the timing of the IC internal synchronization free-running counter matches the timing of the received BIC, the
protection count is incremented by 1. Contrarily, if the timings of the IC internal counter and the received BIC do not
match, the protection counter is cleared to 0. The timing of the count is the timing of the IC internal counter.
Forward protection mode (synchronized: BLOCK=high)
In reverse to the back protection mode, if the timing of the IC internal free-running counter does not match the
detection timing of the received BIC, the protection counter is incremented, and if the timings match, the protection
counter is cleared to 0.
Figure 1 shows the states of the protection counter for the cases where the forward and back protection counts are both
3. This IC defines the value of the protection counter to be 1 at the point that a match or a discrepancy occures between
the IC internal timing and the timing of the received BIC. For example, when the value of the back protection count is
2, the IC internal timing and the timing of the received BIC will have matched two times consecutively.
If the protection data is set to new values, for example if the protection counts are set to 3 as assumed in figure 1,
applications must send values which are 1 less than the intended value; in this case 22H. Similarly, if the value is set to
00H, the protection counts will, by definition, be set to 1 for both the forward and back directions. However, note that
the resulting operation will be equivalent to there being no protection circuit. The default values are 8 for the forward
protection count and 2 for the back protection count.
If the block synchronization output (BLOCK) is used for discriminating whether or not FM multiplex data is present,
we recommend setting the block synchronization back protection count to a value that is more strict than the default
value. (That is, we recommend replacing the default value of 2 with a value of 3 or higher.)
Figure 1 Block Synchronization Protection Operation (Forward →
→
→ Back →
→
→ Forward)
0
1
0
3
2
1
3
2
1
Reset
BIC
Received data
Synchronization
counter BIC position
* Assumes that the forward and
back protection counts are 3.
Block
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