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參數資料
| 型號： | LC72713W |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數： | 8/22頁 |
| 文件大小： | 201K |
| 代理商： | LC72713W |
LC72713W
No.6870-16/29
Notes on Operation during Resets and in Standby Mode
Reset Signal
The reset operation is executed when the supply voltage (VDD) rises above 3.4V (2.5V in the LC72710LW) and the
RST pin input level is held at or below VIL for 300ns or longer. (See the figure below.)
When power is first applied, or when power is removed and applied again, always apply a reset before using this IC.
Pin States during Reset
Low level:CLK16 (5), DATA (6), FLOCK (7), BLOCK (8), FCK (9), BCK (10)
High level: INT (33), RDY (16), CRC4 (11), DREQ (12)
Open: D0 (17) to D15 (32), DO (36)
Reset Operating Range
The states of the output pins as the result of a reset signal are stipulated in the "Pin States during Reset" item above.
The IC internal flip-flops are all reset. While the shift registers used for delay are also reset, the memory array is not
influenced by this operation. However, since memory is not refreshed, data cannot be retained. The crystal oscillator
circuit is not stopped.
Post-Reset Data Input
After a reset operation has completed, if at least one clock cycle (about 278ns when the IC's main clock is 3.6MHz)
elapses, the register write circuit will be functional. (That is, the IC can accept data.)
Notes on Standby Mode
The IC is set to standby mode by applying a high level to the STNBY pin. Since all IC operations are stopped in this
mode, the state is essentially equivalent to removing power from the IC. (Note that after clearing standby mode,
applications must wait the oscillator stabilization time before using the IC.)
The pin output states during standby mode are the same as those states during a reset as described above. The
internal VICS registers are cleared and the status flag values are not retained.
Output Conditions for Post-Error Correction Output (Default Mode)
(1) For each block (272 bits) of received data, the IC applies (272, 190) code error correction and a layer 2 CRC
error check. After the error correction has completed, the IC prepares to transfer the data to the CPU and
outputs an interrupt signal from the INT pin. This is referred to as horizontal correction output.
(2) Note that under the default operating conditions, this interrupt signal is not output unless the corresponding
output data meets the following three conditions.
Error correction completed correctly and no errors were discovered in the layer 2 CRC check.
The data was received in both block and frame synchronization.
The data is packet data.
(3) If the data could not be corrected in horizontal correction, product code correction is performed in frame units
and a second horizontal correction operation is performed for this data that could not be corrected by the first
horizontal correction. This sequence of operations is called vertical correction.
The output conditions for data that can be acquired after vertical correction are as follows.
The data that could not be corrected by horizontal correction only, but that was corrected by vertical
correction.
The data is packet data.
Continued on next page.
RST
3.4V
VIL(0.3VDD)
VIH
300ns(min)
VDD voltage
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