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參數(shù)資料
| 型號(hào)： | LC7471 |
| 元件分類(lèi)： | 畫(huà)面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDIP22 |
| 封裝： | SHRINK, DIP-22 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 134K |
| 代理商： | LC7471 |
LC7471
No.4088–4/12
Timing Characteristics at Ta = –30 to +75C, VDD1 = 5±0.5V
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Input Timing
Data and address words are input in serial format on SIN.
A 16-bit address word followed by 16-bit data words is
input after the falling edge of CS. The address automati-
cally increments after each data word. The data input tim-
ing is shown in the following figure.
Only the lower eight bits of the address word are signifi-
cant. Only the lower eight bits of data words at addresses
000H to 0AFH, the lower 11 bits of data words at
addresses 0B0H to 0BBH and the lower 12 bits of data
words at addresses 0BCH to 0BFH are significant. All
non-significant bits should be set to 0.
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