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參數資料
| 型號： | LC74725M |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDSO24 |
| 封裝： | 0.375 INCH, PLASTIC, MFP-24 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 330K |
| 代理商： | LC74725M |
No. 5213-4/16
LC74725, 74725M
Continued from preceding page.
Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 V ± 0.5 V
Note: Follows the OSD timing for the CMOS output circuit type.
Figure 1 OSD Serial Data Input Timing
Parameter
Symbol
Conditions
min
typ
max
Unit
Border level 0
VBK0
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
1.43
1.55
1.67
V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
1.61
1.73
1.85
V
Border level 1
VBK1
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
2.01
2.13
2.25
V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
2.18
2.30
2.42
V
Character level
VCHA
When the sync level is 0.8 V, CVOUT: VDD1, VDD2 = 5 V
2.57
2.69
2.81
V
When the sync level is 1.0 V, CVOUT: VDD1, VDD2 = 5 V
2.76
2.88
3.00
V
Parameter
Symbol
Conditions
min
typ
max
Unit
OSD write (See Figure 1.)
Minimum input pulse width
tW (SCLK)
SCLK
200
ns
tW (CS1)
CS1 (the period when CS1 is high)
1
s
Data setup time
tSU (CS1)
CS1
200
ns
tSU (SIN)
SIN
200
ns
Data hold time
th (CS1)
CS1
2
s
th (SIN)
SIN
200
ns
One-word write time
tword
The time to write 8 bits of data
4.2
s
twt
The RAM data write time
1
s
ESD read (See Figure 2 for the n-channel open-drain circuit.)
tCKCY
SCLK
2
ns
Minimum input pulse width
tCKL
SCLK
1
s
tCKH
SCLK
1
s
Data setup time
tICK
SCLK
10
s
Output delay time
tCKO
CPDT
0.5
s
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