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參數資料
| 型號： | LC74781M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 183K |
| 代理商： | LC74781M |
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified
Note: 1. When the sync level is 0.8 V.
2. When the sync level is 1.0 V.
Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ± 0.5 V
No. 4988-4/16
LC74781, 74781M
Parameter
Symbol
Conditions
min
typ
max
Unit
Input off leakage current
Ileak1
CVIN pin
1
A
Output off leakage current
Ileak2
CVOUT pin
1
A
Output high level voltage
VOH1
BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V,
3.5
V
IOH = –1.0 mA
Output low level voltage
VOL1
BLANK, CHARA and SEPOUT pins: VDD1 = 4.5 V,
1.0
V
IOH = 1.0 mA
Input current
IIH
RST, CS, SIN, SCLK, CTRL1, CTRL3 and SEPIN pins:
1
A
VIN = VDD1
IIL
CTRL1, CTRL2, CTRL3 and OSCIN pins: VIN = VSS1
–1
A
Operating current drain
IDD1
VDD1 pin; all outputs: open, Xtal: 7.159 MHz,
15
mA
LC: 8 MHz
IDD2
VDD2 pin: VDD2 = 5 V
20
mA
Sync level
VSN
CVOUT pin
VDD1 = 5.0 V,
*1
0.70
0.82
0.94
V
VDD2 = 5.0 V
*2
0.91
1.03
1.15
V
Pedestal level
VPD
CVOUT pin
VDD1 = 5.0 V,
*1
1.31
1.43
1.55
V
VDD2 = 5.0 V
*2
1.53
1.65
1.77
V
Color burst low level
VCBL
CVOUT pin
VDD1 = 5.0 V,
*1
1.00
1.12
1.24
V
VDD2 = 5.0 V
*2
1.21
1.33
1.45
V
Color burst high level
VCBH
CVOUT pin
VDD1 = 5.0 V,
*1
1.63
1.75
1.87
V
VDD2 = 5.0 V
*2
1.84
1.96
2.08
V
Background color low level
VRSL
CVOUT pin
VDD1 = 5.0 V,
*1
1.47
1.59
1.71
V
VDD2 = 5.0 V
*2
1.68
1.80
1.92
V
Background color high level
VRSH
CVOUT pin
VDD1 = 5.0 V,
*1
1.99
2.11
2.23
V
VDD2 = 5.0 V
*2
2.19
2.31
2.43
V
Border level 0
VBK0
CVOUT pin
VDD1 = 5.0 V,
*1
1.42
1.54
1.66
V
VDD2 = 5.0 V
*2
1.63
1.75
1.87
V
Border level 1
VBK1
CVOUT pin
VDD1 = 5.0 V,
*1
1.99
2.11
2.23
V
VDD2 = 5.0 V
*2
2.19
2.31
2.43
V
Character level
VCHA
CVOUT pin
VDD1 = 5.0 V,
*1
2.58
2.70
2.82
V
VDD2 = 5.0 V
*2
2.78
2.90
3.02
V
Parameter
Symbol
Conditions
min
typ
max
Unit
Minimum input pulse width
tW (SCLK)
SCLK pin
200
ns
tW (CS)
CS pin (the period when CS is high)
1
s
Data setup time
tSU (CS)
CS pin
200
ns
tSU (SIN)
SIN pin
200
ns
Data hold time
th (CS)
CS pin
2
s
th (SIN)
SIN pin
200
ns
One word write time
tword
8-bit data write time
4.2
s
twt
RAM data write time
1
s
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