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參數資料
型號: LC74799
元件分類: 畫面疊加
英文描述: ON-SCREEN DISPLAY IC, PDIP30
封裝: 0.400 INCH, SDIP-30
文件頁數: 23/32頁
文件大?。?/td> 322K
代理商: LC74799
No. 5834-3/32
LC74799, 74799M
Pin Descriptions
Pin No.
Pin name
Function
Notes
Ground
Ground connection (digital system ground)
1
VSS1
Crystal oscillator
(MUTE input)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an
external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to
function as the MUTE input pin. When this pin is set low, the video output is held at the
pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)
Crystal oscillator input switching
(CHABLK output)
Switches the mode between external clock input and crystal oscillator operation. A low
level selects crystal oscillator operation and a high level selects external clock input. As a
mask option, the CTRL1 input pin can be set to function as the CHABLK (character
frame) output. This is a 3-value output.
2
XtalIN
3
XtalOUT
(MUTE)
4
CTRL1
(CHABLK)
This pin must be left open.
5NC
Clock input
Input for the PDC/VPS data output clock. I2C bus
6
SCL
Data output
PDC/VPS data output.
I2C bus write address: [01111100]
I2C bus read address: [01111101]
7
SDA
External synchronizing signal judgment
output
Outputs the state of the external synchronizing signal presence/absence judgment.
Outputs a high level when synchronizing signals are present.
Outputs the crystal oscillator clock when CS1 and RST are low.
(This signal is not output on command resets.)
8
SYNCJDG
Enable input 1
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
9
CS1
Clock input 1
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
10
SCLK1
Data input 1
Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics.
11
SIN1
Power supply
Composite video signal level adjustment power supply (analog system power supply)
12
VDD2
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
13
CPOUT
Oscillator control voltage input
VCO oscillator control voltage input. (For data slicing)
14
VCOIN
Ground
Ground (VCO ground)
15
VSS3
Oscillator range adjustment
VCO oscillator range adjustment resistor connection
16
VCOR
Oscillator control voltage input 2
VCO oscillator control voltage input. For character display.
17
VCOIN2
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
18
VDD3
Video signal output
Composite video signal output
19
CVOUT
Ground
Ground (analog system ground)
20
VSS2
Video signal input
Composite video signal input
21
CVIN
Video signal input
SECAM chrominance signal input
22
CVCR
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
23
VDD1
Sync separator circuit input
Video signal input to the internal sync separator circuit
24
SYNIN
Sync separator circuit adjustment
Internal sync separator circuit adjustment
25
SEPC
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output. Can be switched to
function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is
high.
26
SEPOUT
Vertical synchronizing signal input
Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output
signal.
An integration circuit must be connected between this pin and the SEPOUT pin. This pin
must be tied to VDD1 if unused. This pin is valid when CTL3 is set high.
27
SEPIN
Background color phase adjustment
Background color phase adjustment resistor connection
28
CDLR
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
29
RST
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
30
VDD1
Note *: A capacitor of at least 2000 pF must be connected between the VDD1 power supply and VSS1.
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