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參數資料
| 型號： | LC78647NT |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁數： | 2/17頁 |
| 文件大小： | 175K |
| 代理商： | LC78647NT |
LC78647NT
-10-
Pin
No.
Pin Name
I/O
State after
Reset
Function
45
LVDD
—
L channel power supply pin
46
LCHO
AO
LVDD /2
L channel output pin
47
LVSS
—
For L channel audio
L channel ground pin. Must be connected to 0V.
48
RVSS
—
R channel ground pin. Must be connected to 0V.
49
RCHO
AO
LVDD /2
R channel output pin
50
RVDD
—
For R channel audio
R channel power supply pin
51
XVDD
—
Crystal oscillation power supply pin
52
XOUT
O
Oscillation
53
XIN
I
Oscillation
For crystal
oscillation
16.9344 MHz resonator connection pins
54
FSX/16MIN
I/O
Input mode 7.35 kHz synchronization signal output pin, or DF/DAC external clock input pin
55
XVSS
—
For crystal
oscillation
Crystal oscillation ground pin. Must be connected to 0V.
56
16MOUT
O
CLK output 16.9344 MHz output pin
57
C2F/EFLG
O
H
C2 flag output pin (in reset). C1, C2 correction monitor pin
58
LRSY
O
L
L/R clock output pin
59
DATACK
O
L
Bit clock output pin
60
DATA
O
L
For digital data
output
L/R channel data output pin
61 CE
I
—
Chip enable signal input pin
62
CL
I
—
Data transfer clock input pin
63
DI
I
—
Data input pin
64
DO
O
(H)
Data output pin (Nch open-drain output)
65
WRQB
O
H
For microcomputer
interface
Interrupt signal output pin
66
RESB
I
—
LC78647NT IC reset input pin. Drive to “L” level at power-on.
67
DRF
O
L
Focus ON detection pin
68
WOK/
ASLRCK
I—
DRAM write enable signal input. “H”: Write enabled
L/R clock input pin
69
OVF/
ASDACK
I/O
—
DRAM write suspension
Bit clock input pin. ASDACK input mode after reset
70
CNTOK/
ASDFIN
I/O
—
Data connection point detection completed signal
L/R channel data input pin. ASDFIN input mode after reset
71
VSS
—
Digital ground pin. Must be connected to 0V.
72
OEB
O
H
DRAM control signal output pin
73
CASB
O
H
DRAM control signal output pin
74
RAMD2
I/O
—
DRAM data I/O pin
75
RAMD3
I/O
—
DRAM data I/O pin
76
MVSS
—
DRAM I/F ground pin. Must be connected to 0V.
77
MVDD
—
DRAM I/F power supply pin
78
RAMD0
I/O
—
DRAM data I/O pin
79
RAMD1
I/O
—
DRAM data I/O pin
80
WEB
O
H
DRAM control signal output pin
81
RASB
O
H
DRAM control signal output pin
82
A11
O
L
DRAM address output pin
83
A10
O
L
DRAM address output pin
84
A9
O
L
DRAM address output pin
85
A8
O
L
DRAM address output pin
86
A7
O
L
DRAM address output pin
87
A6
O
L
DRAM address output pin
88
A5
O
L
DRAM address output pin
89
A4
O
L
DRAM address output pin
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