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參數資料
| 型號： | LC82102W |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | SQFP-64 |
| 文件頁數： | 5/5頁 |
| 文件大小： | 74K |
| 代理商： | LC82102W |
PS No. 5155-5/5
LC82102, LC82102W
This catalog provides information as of September, 1995. Specifications and information herein are subject to
change without notice.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Sample Application
1. C1: Use a 0.01 F laminated ceramic capacitor.
2. Set up the polarity of the image signal from the sensor so that white data is represented by the highest potential and
black data by the lowest potential. A level conversion circuit can allow the whole dynamic range of the built-in A/D
converter to be used effectively if the maximum output level of the peaks in the image signal from the sensor does
not reach 4.2 V.
3. Although AGND and DGND are completely isolated internally in this LSI, AVDD and DVDD are connected through
the substrate. Therefore, the power supply system must be designed so that no potential difference between AVDD
and DVDD can occur. Also, when power is applied or removed, the time lag between the power supplies must be
under 3 ms.
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