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參數資料

型號：	LC890561W
廠商：	SANYO SEMICONDUCTOR CO LTD
元件分類：	消費家電
英文描述：	SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝：	7 X 7 MM, SQFP-48
文件頁數：	20/47頁
文件大小：	357K
代理商：	LC890561W

LC890561W

No8226-27/47

13.2.2 Output Data Delay Setup after Recovery Processing (Setting at the state of ERROR = L)

When the DTMA[4:0], DTMB[3:0] and DTMC[2:0] commands are set up or changed during L output of ERROR flag,

delay processing is performed according to the setup of those commands.

After power up, when the command is set up for the first time, a memory domain is assigned according to the set

delay, and data is written in a memory.

A memory domain is reset when the delay time is changed in the state where the command is already set up. And a

memory domain is assigned according to the newly set-up delay time, and the data writing to a memory is started.

Readout of the data written in the memory is started after the set delay time (frame).

DATAO output is muted immediately after the command setup until the end of the set delay time.

Figure 13.3 Timing Chart for Output Data after Setup or Change of the Delay Time During PLL Lock

When delay time is canceled in the state where the command is already set up, the writing to the memory is stopped.

However, DATAO is output after muting the input data for 512-frame period. DATAO is not output immediately after

cancel of command setting. The 512-frame period is dependent on the sampling frequency of input data.

Figure 13.4 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Locked

When the command is changed before the completion of command setting, the delay process is initialized every

command setting. For DATAO output, mute output is continued until the setting is fixed.

ERROR

DATAO

Ln-a Rn-a

Delay time (70ms)

DATAO2

Rn+1

Rn+a

Ln+1

Ln+b

XSTATE

(XSTP = 0)

0 data (mute)

Rm-1

Lm-1

Rn+2

Ln+2

Ln+3

Rn+b Ln+c Rn+c

LRCK

Delay time

Setting of

ex.) Delay = 50ms

ex.) Delay = 70ms

Rn-1

Ln-1

Rm-2

Lm-2