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參數資料
| 型號： | LE57D113JC |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數： | 11/22頁 |
| 文件大小： | 546K |
| 代理商： | LE57D113JC |
P R E L I M I N A R Y
Le57D11 Data Sheet
11
Note:
1.
Unless otherwise noted, test conditions are BAT = –52 V; V
CC
= +5 V; R
L1
, R
L2
= 600
; R
TMG1
, R
TMG2
= 1600
; no fuse resistors; C
HP1
,
C
HP2
= 100 nF; C
DC1
,C
DC2
= 1.5 μF; C
CAS
= 0.33 μF; R
REF
=15 K; two-wire AC input impedance is a 600
resistance synthesized by the
programming network shown below.
Figure 3.
AC Input Impedance Programming Network
2.
a. Z when THD = 1%.
b. Overload level is defined when THD = 1.5%.
3.
Balance return signal is the signal generated at V
TX
by V
RX
. This specification assumes that the two-wire, AC-load impedance matches the
programmed impedance.
4.
Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5.
This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6.
Tested with 0
source impedance. 2 M
is specified for system design only.
7.
Group delay can be greatly reduced by using a Z
T
network such as that shown in Note 1. The network reduces the group delay to less than
2 μs and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing complex
impedance with the QSLAC or DSLAC device.
8.
Minimum current level guaranteed not to cause a false loop detect.
SLIC Decoding
(For X, Channel = 1 or 2)
State
C2x
C1x
Two-Wire Status
DETx output
0
0
0
Disconnect
Ring-Trip Detector
1
0
1
Active
Loop Detector
2
1
1
Polarity Reversed
Loop Detector
3
1
0
Standby
Loop Detector
VTX
R
T1
= 41.7 k
R
T2
= 41.7 k
C
T1
= 120 pF
R
RX
= 124 k
V
RX
RSN
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