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參數資料
| 型號： | LE57D113JC |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數： | 15/22頁 |
| 文件大?。?/td> | 546K |
| 代理商： | LE57D113JC |
P R E L I M I N A R Y
Le57D11 Data Sheet
15
Figure 7.
Longitudinal Balance
Figure 8.
Two-Wire Return Loss Test Circuit
Figure 9.
RFI Test Circuit
SLIC
AGND
V
AB
R
T
R
RX
L-T Long. Bal. = 20 log(V
AB
/ V
L
)
L-4 Long. Bal. = 20 log(V
TX
/ V
L
)
V
RX
R
L
2
R
L
2
V
L
V
L
S1
1
ω
C
R
L
<<
S2
S2 Open, S1 Closed
S2 Closed, S1Open
4-L Long. Sig. Gen. = 20 log(V
L
/ V
RX
)
C
A
1
, A
2
(TIP)
B
1
, B
2
(RING)
VTX
1
VTX
2
RSN
1
RSN
2
Return loss = –20 log (2V
M
/ V
S
)
Z
: The desired impedance;
eg., the characteristic impedance of the line
SLIC
AGND
R
RX
= 124 K
C
T
= 120 pF
R
TA
R
TB
V
M
V
S
R
R
41.7 K
41.7 K
Z
D
= 600
300
300
Z
IN
= 600
A
1
, A
2
(TIP)
B
1
, B
2
(RING)
VTX
1
VTX
2
RSN
1
RSN
2
HF
GEN
L
1
L
2
200
200
C
1
C
2
50
50
RF
1
RF
2
C
AX
C
BX
SLIC
under test
80% amplitude modulated
Modulation frequency = 1 kHz
50
VTX
1
VTX
2
A
1
, A
2
(TIP)
B
1
, B
2
(RING)
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