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參數資料
型號: LM1267NA/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 音頻/視頻放大
英文描述: 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24
封裝: PLASTIC, DIP-24
文件頁數: 11/20頁
文件大?。?/td> 1702K
代理商: LM1267NA/NOPB
DAC Interface Register Definitions
(Continued)
Register name: DAC 3 (06h)
Bit 7
Bit 0
D3–7 D3–6 D3–5 D3–4 D3–3 D3–2 D3–1 D3–0
Bits 7–0: DAC 3. These eight bits determine the output
voltage of DAC 3.
DAC 4 Register (I
2C address 07h)
Register name: DAC 4 (07h)
Bit 7
Bit 0
D4–7 D4–6 D4–5 D4–4 D4–3 D4–2 D4–1 D4–0
Bits 7–0: DAC 4. These eight bits determine the output
voltage of DAC 4.
DC Offset and OSD Contrast Control Register (I
2C ad-
dress 08h)
Register name: DC Offset/OSD Cont. (08h)
Bit 7
Bit 0
RSV
OSDC1
OSDC0
DC2
DC1
DC0
Bits 2–0: DC Offset Control. These three bits determine the
active video DC offset to all three channels.
Bits 4–3: OSD Contrast Control. These two bits determine
the contrast level of the OSD information.
Bits 7–5: Reserved.
Global Video Control Register (I
2C address 09h)
Register name: Global Control (09h)
Bit 7
Bit 0
RSV
0
DCF4
DCF1–3
0
PS
BV
Bit 0:
Blank Video. When this bit is a one, blank the
video output. When this bit is a zero allow normal
video out.
Bit 1:
Power Save. When this bit is a one, shut down
the analog circuits to support sleep mode. When
this bit is a zero enable the analog circuits for
normal operation.
Bit 2:
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Bit 3:
DAC1–3 Configuration. When this bit is a zero
the DAC outputs of DAC1–3 are full scale
(0V–4.5V). When this bit is 1, the range of
DAC1–3 are halved (0V–2.25V).
Bit 4:
DAC4 Configuration. When this bit is a zero the
DAC4 output is not mixed with the other DAC
outputs. When the bit is one, 50% of the DAC4
output is added to DAC1–3.
Bit 5:
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Bits 7–6: Reserved.
Increment Mode Register (I
2C address 0Ah)
Register name: Increment Mode (0Ah)
Bit 7
Bit 0
RSV
TST
INCR
Bit 0:
Increment Enable. When set to a “0”, the default
value, the increment mode is enabled. This al-
lows the registers to be updated sequentially by
sending another block of data.
Bit 1:
MUST BE SET TO “0” FOR PROPER OPERA-
TION.
Bits 7–2: Reserved.
Clamp Polarity and Bandwidth (I
2C address 0Bh)
Register name: Clamp/BW (0Bh)
Bit 7
Bit 0
RSV
CLMP
BW1
BW2
BW0
Bits 2–0: Bandwidth. Used to set the bandwidth of the
preamp. The default is 100. When all bits are set
to “1”, the LM1267 will have maximum bandwidth,
when all bits are set to “0” the LM1267 will have
minimum bandwidth.
Bit 3:
Determines the polarity of the clamp signal used
by the LM1267, “0” (default) is a positive clamp
signal, “1” is a negative going clamp signal.
Bits 7–4: Reserved.
Software Reset Register (I
2C address 0Fh)
Register name: Software Reset (0Fh)
Bit 7
Bit 0
RSV
SRST
Bit 0:
Software Reset. Setting this bit causes a software
reset. All registers (except this one) are loaded
with their default values. All operations currently
in progress are aborted (except for I
2C transac-
tions). This bit automatically clears itself when the
reset has been completed.
Bits 7–1: Reserved.
LM1267
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相關代理商/技術參數
參數描述
LM1269 制造商:NSC 制造商全稱:National Semiconductor 功能描述:110 MHz I2C Compatible RGB Video Amplifier System with OSD & DACs
LM1269DNA 制造商:Texas Instruments 功能描述:
LM1269DNA/NOPB 功能描述:IC PREAMP CMOS 110MHZ 24-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調諧器 應用:移動電話,手機,視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
LM1269NA 制造商:Texas Instruments 功能描述:Video Amplifiers 制造商:Texas Instruments 功能描述:-LIFETIME BUYS TIL 05/12
LM1269NA/NOPB 功能描述:視頻放大器 RoHS:否 制造商:ON Semiconductor 通道數量:4 電源類型: 工作電源電壓:3.3 V, 5 V 電源電流: 最小工作溫度: 最大工作溫度: 封裝 / 箱體:TSSOP-14 封裝:Reel
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