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參數資料
| 型號： | LM1882RJ/883 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 236K |
| 代理商： | LM1882RJ/883 |
TLF10137
LM1882
54ACT74ACT715
LM1882-R
54ACT74ACT715-R
Programmable
Video
Sync
Generator
March 1995
LM1882
54ACT74ACT715
LM1882-R
54ACT74ACT715-R
Programmable Video Sync Generator
General Description
The ’ACT715LM1882 and ’ACT715-RLM1882-R are
20-pin TTL-input compatible devices capable of generating
Horizontal Vertical and Composite Sync and Blank signals
for televisions and monitors All pulse widths are completely
definable by the user The devices are capable of generat-
ing signals for both interlaced and noninterlaced modes of
operation Equalization and serration pulses can be intro-
duced into the Composite Sync signal when needed
Four additional signals can also be made available when
Composite Sync or Blank are used These signals can be
used to generate horizontal or vertical gating pulses cursor
position or vertical Interrupt signal
These devices make no assumptions concerning the sys-
tem architecture Line rate and fieldframe rate are all a
function of the values programmed into the data registers
the status register and the input clock frequency
The ’ACT715LM1882 is mask programmed to default to a
Clock Disable state Bit 10 of the Status Register Register
0 defaults to a logic ‘‘0’’ This facilitates (re)programming
before operation
The
’ACT715-RLM1882-R
is
the
same
as
the
’ACT715LM1882
in
all
respects
except
that
the
’ACT715-RLM1882-R is mask programmed to default to a
Clock Enabled state Bit 10 of the Status Register defaults
to a logic ‘‘1’’ Although completely (re)programmable the
’ACT715-RLM1882-R version is better suited for applica-
tions using the default 1431818 MHz RS-170 register val-
ues This feature allows power-up directly into operation
following a single CLEAR pulse
Features
Y
Maximum Input Clock Frequency l 130 MHz
Y
Interlaced and non-interlaced formats available
Y
Separate or composite horizontal and vertical Sync and
Blank signals available
Y
Complete control of pulse width via register
programming
Y
All inputs are TTL compatible
Y
8 mA drive on all outputs
Y
Default RS170NTSC values mask programmed into
registers
Y
4 KV minimum ESD immunity
Y
’ACT715-RLM1882-R is mask programmed to default
to a Clock Enable state for easier start-up into
1431818 MHz RS170 timing
Connection Diagrams
Pin Assignment for
DIP and SOIC
TLF10137 – 1
Order Number LM1882CN or LM1882CM
For Default RS-170 Order Number LM1882-RCN or
LM1882-RCM
Pin Assignment
for LCC
TLF10137 – 2
TRI-STATE
is a registered trademark of National Semiconductor Corporation
FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A
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