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參數資料
| 型號： | LM1882RJ/883 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數： | 2/16頁 |
| 文件大?。?/td> | 236K |
| 代理商： | LM1882RJ/883 |
AC Electrical Characteristics
ACTLM1882
54ACTLM1882
74ACTLM1882
VCC
TA ea25 C
TA eb55 CTA eb40 C
Symbol
Parameter
(V)
CL e 50 pF
to a125 Cto a85 C
Units
CL e 50 pF
Min
Typ
Max
Min
Max
Min
Max
fMAXI
Interlaced fMAX
50
170
190
130
150
MHz
(HMAX2 is ODD)
fMAX
Non-Interlaced fMAX
50
190
220
145
175
MHz
(HMAX2 is EVEN)
tPLH1
Clock to Any Output
50
40
130
155
35
195
35
185
ns
tPHL1
tPLH2
Clock to ODDEVEN
50
45
150
170
35
220
35
205
ns
tPHL2
(Scan Mode)
tPLH3
Load to Outputs
50
40
115
160
30
200
30
195
ns
AC Operating Requirements
ACTLM1882
54ACTLM1882
74ACTLM1882
Symbol
Parameter
VCC
TA ea25 C
TA eb55 CTA eb40 C
Units
(V)
to a125 Cto a85 C
Typ
Guaranteed Minimums
Control Setup Time
tsc
ADDRDATA to LOADb
50
30
40
45
ns
tsc
LHBYTE to LOADb
30
40
45
ns
Data Setup Time
tsd
D7 – D0 to LOADa
50
20
40
45
ns
Control Hold Time
thc
LOADb to ADDRDATA
50
0
10
ns
LOADb to LHBYTE
0
10
ns
Data Hold Time
thd
LOADa to D7 – D0
50
10
20
ns
trec
LOADa to CLK (Note 1)
50
55
70
80
ns
Load Pulse Width
twldb
LOW
50
30
55
ns
twlda
HIGH
50
30
50
75
ns
twclr
CLR Pulse Width HIGH
50
55
65
95
ns
twck
CLOCK Pulse Width
50
25
30
40
35
ns
(HIGH or LOW)
Note 1
Removal of Vectored Reset or Restart to Clock
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
70
pF
VCC e 50V
CPD
Power Dissipation
170
pF
VCC e 50V
Capacitance
10
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