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參數資料
| 型號： | LM78 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Microprocessor System Hardware Monitor |
| 中文描述： | 微處理器系統硬件監視器 |
| 文件頁數： | 25/31頁 |
| 文件大小： | 424K |
| 代理商： | LM78 |
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Functional Description
(Continued)
13.2 Data Register (Port x6h)
Power on default
<
7:0
>
= 00h
Bit
Name
Read/
Write
Read/Write
Description
7–0
Data
Data to be read from or to be written to RAM and Register.
13.3 Configuration Register—Address 40h
Power on default
<
7:0
>
= 00001000 binary
Bit
Name
Read/
Write
Read/Write
Description
0
Start
A one enables startup of monitoring operations, a zero puts the part in standby mode.
Note:
The outputs of Interrupt pins will not be cleared if the user writes a zero to this
location after an interrupt has occurred unlike “INT__Clear” bit.
A one enables the SMI Interrupt output.
A one enables the NMI/IRQ Interrupt output.
1
2
SMI Enable
NMI/IRQ
Enable
INT__Clear
Read/Write
Read/Write
3
Read/Write
A one disables the SMI and NMI/IRQ outputs without affecting the contents of Interrupt
Status Registers. The device will stop monitoring. It will resume upon clearing of this
bit.
A one outputs at least a 20 ms active low reset signal at RESET if
<
7
>
= 1 in SMI
Mask Register 2. This bit is cleared once the pulse has gone inactive.
A one selects NMI, and a zero selects IRQ.
4
RESET
Read/Write
5
NMI/IRQ
Select
Power Switch
Bypass
INITIALIZATION
Read/Write
6
Read/Write
A one in this bit drives a zero on Power Switch Bypass pin.
7
Read/Write
A one restores power on default value to all registers
except
the Serial Bus Address
register. This bit clears itself since the power on default is zero.
L
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