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參數資料
| 型號： | LM78 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Microprocessor System Hardware Monitor |
| 中文描述： | 微處理器系統硬件監視器 |
| 文件頁數： | 26/31頁 |
| 文件大小： | 424K |
| 代理商： | LM78 |
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Functional Description
(Continued)
13.4 Interrupt Status Register 1—Address 41h
Power on default
<
7:0
>
= 00h
Bit
0
1
2
3
4
5
Name
IN0
IN1
IN2
IN3
Temperature
BTI
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Description
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates an interrupt has occurred from the Board Temperature Interrupt (BTI)
input (O.S. output of multiple LM75 chips).
A one indicates the fan count limit has been exceeded.
A one indicates the fan count limit has been exceeded.
6
7
FAN1
FAN2
Read Only
Read Only
13.5 Interrupt Status Register 2—Address 42h
Power on default
<
7:0
>
= 00h
Bit
0
1
2
3
4
5
Name
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Description
IN4
-IN5
-IN6
FAN3
Chassis Intrusion
FIFO Overflow
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates the fan count limit has been exceeded.
A one indicates Chassis Intrusion has gone high.
A one indicates an overflow in FIFO (POST RAM) i.e. 32nd location in FIFO has
been written via Port x0h or x4h.
A one indicates SMI__IN has gone low.
6
7
SMI__IN
Reserved
Read Only
Read Only
13.6 SMI Mask Register 1—Address 43h
Power on default
<
7:0
>
= 00h
Bit
Name
Read/
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
0
1
2
3
4
5
6
7
IN0
IN1
IN2
IN3
Temperature
BTI
FAN1
FAN2
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
A one disables the corresponding interrupt status bit for SMI interrupt.
L
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