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參數(shù)資料
| 型號： | LM81 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Interface ACPI-Compatible Microprocessor System |
| 中文描述： | 串行接口ACPI的兼容微處理器系統(tǒng) |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 412K |
| 代理商： | LM81 |
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Functional Description
(Continued)
13.4 Interrupt Status Register 1— Address 41h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
0
1
2
3
4
5
6
7
Name
+2.5Vin
Vccp1
+3.3Vin
+5Vin
Temperature
Reserved
FAN1
FAN2
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Description
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates a HIGH or HIHYST temperature error, see SECTION 8.2
A one indicates the fan count limit has been exceeded.
A one indicates the fan count limit has been exceeded.
13.5 Interrupt Status Register 2— Address 42h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
0
1
2
3
4
5
6
7
Name
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Description
+12Vin
Vccp2
Reserved
Reserved
CI
Reserved
Reserved
TLOW
A one indicates a High or Low limit has been exceeded.
A one indicates a High or Low limit has been exceeded.
A one indicates CI (Chassis Intrusion) has gone high.
A one indicates LOW temperature error in
EXTENDED MODE ONLY
, see
SECTION 8.2
13.6 Interrupt Mask Register 1— Address 43h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
Name
Read/
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
0
1
2
3
4
5
6
7
+2.5Vin
Vccp1
+3.3Vin
+5Vin
Temperature
Reserved
FAN1
FAN2
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
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