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參數(shù)資料
| 型號(hào)： | LMF100ACN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | IC-MONOLITHIC FILTER |
| 中文描述： | DUAL SWITCHED CAPACITOR FILTER, RESISTOR PROGRAMMABLE, UNIVERSAL, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大小： | 868K |
| 代理商： | LMF100ACN |
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3.0 Applications Information
(Continued)
3.1 DESIGN EXAMPLE
In order to design a filter using the LMF100, we must define
the necessary values of three parameters for each
second-order section: f
, the filter section’s center frequency;
H
, the passband gain; and the filter’s Q. These are deter-
mined by the characteristics required of the filter being de-
signed.
As an example, let’s assume that a system requires a
fourth-order Chebyshev low-pass filter with 1 dB ripple, unity
gain at dc, and 1000 Hz cutoff frequency. As the system or-
der is four, it is realizable using both second-order sections
of an LMF100. Many filter design texts (and National’s
Switched Capacitor Filter Handbook) include tables that list
the characteristics (f
and Q) of each of the second-order fil-
ter sections needed to synthesize a given higher-order filter.
For the Chebyshev filter defined above, such a table yields
the following characteristics:
f
0A
= 529 Hz
Q
A
= 0.785
f
0B
= 993 Hz
Q
B
= 3.559
For unity gain at dc, we also specify:
H
0A
= 1
H
0B
= 1
The desired clock-to-cutoff-frequency ratio for the overall fil-
ter of this example is 100 and a 100 kHz clock signal is avail-
able. Note that the required center frequencies for the two
second-order
sections
will
clock-to-center-frequency ratios of 50 or 100. It will be nec-
essary to adjust
not
be
obtainable
with
externally. From Table 1 we see that Mode 3 can be used to
produce a low-pass filter with resistor-adjustable center fre-
quency.
In most filter designs involving multiple second-order stages,
it is best to place the stages with lower Q values ahead of
stages with higher Q, especially when the higher Q is greater
than 0.707. This is due to the higher relative gain at the cen-
ter frequency of a higher-Q stage. Placing a stage with lower
Q ahead of a higher-Q stage will provide some attenuation at
the center frequency and thus help avoid clipping of signals
near this frequency. For this example, stage A has the lower
Q (0.785) so it will be placed ahead of the other stage.
For the first section, we begin the design by choosing a con-
venient value for the input resistance: R
= 20k. The abso-
lute value of the passband gain H
OLPA
is made equal to 1 by
choosing R
such that: R
= H
R
= R
= 20k. If
the 50/100/CL pin is connected to mid-supply for nominal
100:1 clock-to-center-frequency ratio, we find R
2A
by:
The resistors for the second section are found in a similar
fashion:
The complete circuit is shown in Figure 19 for split
±
5V
power supplies. Supply bypass capacitors are highly
recommended.
www.national.com
21
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMF100AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Filter |
| LMF100CCN | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:FILTER DUAL SWITCHED CAP DIP 100 |
| LMF100CCN | 制造商:Texas Instruments 功能描述:FILTER DUAL SWITCHED CAP DIP 100 |
| LMF100CCN/NOPB | 功能描述:IC FILTER DUAL SWITCH CAP 20-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 濾波器類型:連續(xù)時(shí)間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) |
| LMF100CCWM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Filter |
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