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參數資料
| 型號： | LMF100ACN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | IC-MONOLITHIC FILTER |
| 中文描述： | DUAL SWITCHED CAPACITOR FILTER, RESISTOR PROGRAMMABLE, UNIVERSAL, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數： | 8/28頁 |
| 文件大小： | 868K |
| 代理商： | LMF100ACN |
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Pin Descriptions
LP(1,20),
BP(2,19),
N/AP/HP(3,18)
The second order lowpass,
bandpass and
notch/allpass/highpass outputs.
These outputs can typically swing
to within 1V of each supply when
driving a 5 k
load. For optimum
performance, capacitive loading
on these outputs should be
minimized. For signal frequencies
above 15 kHz the capacitance
loading should be kept below
30 pF.
The inverting input of the
summing opamp of each filter.
These are high impedance inputs.
The non-inverting input is
internally tied to AGND so the
opamp can be used only as an
inverting amplifier.
S1 is a signal input pin used in
modes 1b, 4, and 5. The input
impedance is 1/f
CLK
x 1 pF. The
pin should be driven with a source
impedance of less than 1 k
. If
S1 is not driven with a signal it
should be tied to AGND
(mid-supply).
This pin activates a switch that
connects one of the inputs of each
filter’s second summer either to
AGND (S
A/B
tied to V
) or to the
lowpass (LP) output (S
A/B
tied to
V
+
). This offers the flexibility
needed for configuring the filter in
its various modes of operation.
This is both the analog and digital
positive supply.
This pin needs to be tied to V
+
except when the device is to
operate on a single 5V supply and
a TTL level clock is applied. For
5V, TTL operation, V
D+
should be
tied to ground (0V).
Analog and digital negative
supplies. V
A
and V
D
should be
derived from the same source.
They have been brought out
separately so they can be
bypassed by separate capacitors,
if desired. They can also be tied
together externally and bypassed
with a single capacitor.
INV(4,17)
S1(5,16)
S
A/B
(6)
V
A+
(7) (Note 15)
V
D+
(8) (Note 15)
V
A
(14), V
D
(13)
LSh(9)
Level shift pin. This is used to
accommodate various clock levels
with dual or single supply
operation. With dual
±
5V supplies
and CMOS (
±
5V) or TTL (0V–5V)
clock levels, LSh should be tied to
system ground.
For 0V–10V single supply
operation the AGND pin should be
biased at +5V and the LSh pin
should be tied to the system
ground for TTL clock levels. LSh
should be biased at +5V for
±
5V
CMOS clock levels.
The LSh pin is tied to system
ground for
±
2.5V operation. For
single 5V operation the LSh and
V
D
+ pins are tied to system
ground for TTL clock levels.
Clock inputs for the two switched
capacitor filter sections. Unipolar
or bipolar clock levels may be
applied to the CLK inputs
according to the programming
voltage applied to the LSh pin.
The duty cycle of the clock should
be close to 50%, especially when
clock frequencies above 200 kHz
are used. This allows the
maximum time for the internal
opamps to settle, which yields
optimum filter performance.
By tying this pin to V
+
a 50:1 clock
to filter center frequency ratio is
obtained. Tying this pin at
mid-supply (i.e., system ground
with dual supplies) or to V
allows
the filter to operate at a 100:1
clock to center frequency ratio.
This is the analog ground pin.
This pin should be connected to
the system ground for dual supply
operation or biased to mid-supply
for single supply operation. For a
further discussion of mid-supply
biasing techniques see the
Applications Information (Section
3.2). For optimum filter
performance a “clean” ground
must be provided.
CLK(10,11)
50/100(12)
(Note 15)
AGND(15)
Note 15:
This device is pin-for-pin compatible with the MF10 except for the
following changes:
1. Unlike the MF10, the LMF100 has a single positive supply pin (V
A
+).
2. On the LMF100 V
D+
is a control pin and is not the digital positive supply as
on the MF10.
3. Unlike the MF10, the LMF100 does not support the current limiting mode.
When the 50/100 pin is tied to V
the LMF100 will remain in the 100:1 mode.
www.national.com
8
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LMF100AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Filter |
| LMF100CCN | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述:FILTER DUAL SWITCHED CAP DIP 100 |
| LMF100CCN | 制造商:Texas Instruments 功能描述:FILTER DUAL SWITCHED CAP DIP 100 |
| LMF100CCN/NOPB | 功能描述:IC FILTER DUAL SWITCH CAP 20-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 濾波器類型:連續時間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數:4 濾波器階數:8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) |
| LMF100CCWM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Filter |
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