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參數(shù)資料
| 型號： | LMF90CCWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | 4th-Order Elliptic Notch Filter |
| 中文描述： | SWITCHED CAPACITOR FILTER, ELLIPTIC, NOTCH, PDSO14 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-14 |
| 文件頁數(shù)： | 14/22頁 |
| 文件大小： | 411K |
| 代理商： | LMF90CCWM |
2.0 Applications Information
(Continued)
NOISE
Switched-capacitor filters have two kinds of noise at their
outputs. There is a random, ‘‘thermal’’ noise component
whose level is typically on the order of hundreds of micro-
volts. The other kind of noise is digital clock feedthrough.
This will have an amplitude in the vicinity of 50 mV peak-to-
peak. In some applications, the clock noise frequency is so
high compared to the signal frequency that it is unimportant.
In other cases, clock noise may have to be removed from
the output signal with, for example, a passive low-pass filter
at the LMF90’s output pin.
CLOCK FREQUENCY LIMITATIONS
The performance characteristics of a switched-capacitor fil-
ter depend on the switching (clock) frequency. At very low
clock frequencies (below 10 Hz), the time between clock
cycles is relatively long, and small parasitic leakage currents
cause the internal capacitors to discharge sufficiently to af-
fect the filter’s offset voltage and gain. This effect becomes
more pronounced at elevated operating temperatures.
At higher clock frequencies, performance deviations are pri-
marily due to the reduced time available for the internal op-
erational amplifiers to settle. Best performance with high
clock frequencies will be obtained when the filter clock’s
duty cycle is 50%. The clock frequency divider, when used,
provides a 50% duty cycle clock to the filter, but when an
external clock is applied to CLK, it should have a duty cycle
close to 50% for best performance.
Input Impedance
The input to the bandpass section of the LMF90 (V
IN1
) is
similar to the switched-capacitor circuit shown in Figure 5.
During the first half of a clock cycle, the
i
1
switch closes,
charging C
IN
to the input voltage V
IN
. During the second
half-cycle, the
i
2
switch closes, and the charge on C
IN
is
transferred to the feedback capacitor. At frequencies well
below the clock frequency, the input impedance approxi-
mates a resistor whose value is
R
IN
e
1
C
IN
f
CLK
.
At the bandpass filter input, C
IN
is nominally 3.0 pF. For a
worst-case calculation of effective R
IN
, assume C
IN
e
3.0 pF and f
CLK
e
1.5 MHz. Thus,
R
IN
(Min)
e
1
4.5 x 10
b
6
e
222 k
X
.
At the maximum clock frequency of 1.5 MHz, the lowest
typical value for the effective R
IN
at the V
IN1
input is there-
fore 222 k
X
. Note that R
IN
increases as f
CLK
decreases, so
the input impedance will be greater than or equal to this
value. Source impedance should be low enough that this
input impedance doesn’t significantly affect gain.
The summing amplifier input impedance at V
IN2
is calculat-
ed in a similar manner, except that C
IN
e
5.0 pF. This yields
a minimum input impedance of 133 k
X
at V
IN2
. When both
inputs are connected together, the combined input imped-
ance will be 83.3 k
X
with a 1.5 MHz filter clock.
TL/H/10354–9
FIGURE 5. Simplified LMF90 bandpass section input
stage. At frequencies well below the center frequency,
the input impedance appears to be resistive.
2.5 POWER SUPPLY AND CLOCK OPTIONS
The LMF90 is designed to operate from either single or dual
power supply voltages from 5V to 15V. In either case, the
supply pins should be well-bypassed to minimize any feed-
through of power supply noise into the filter’s signal path.
Such feedthrough can significantly reduce the depth of the
notch. For operation from dual supply voltages, connect V
b
(pin 8) to the negative supply, GND (pin 13) to the system
ground, and V
to the positive supply.
For single supply operation, simply connect V
b
to system
ground and GND (Pin 13) to a ‘‘clean’’ reference voltage at
mid-supply. This reference voltage can be developed with a
pair of resistors and a capacitor as shown in Figures 10
through16. Note that for single supply operation, the three-
level logic inputs should be connected to system ground
and V
/2 instead of V
and GND. The CLK input will oper-
ate properly with TTL-level clock signals when the LMF90 is
powered from either single or dual supplies because it has
two TTL thresholds, one referred to the V
pin and one
referred to the GND pin. XLS should be connected to the
V
pin when an external TTL clock is used. Figures 6
through 16 illustrate a wide variety of power supply and
clock options.
14
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相關(guān)代理商/技術(shù)參數(shù) |
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| LMF90CIJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4th-Order Elliptic Notch Filter |
| LMF90CIN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4th-Order Elliptic Notch Filter |
| LMF90CIWM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4th-Order Elliptic Notch Filter |
| LMF90CMJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4th-Order Elliptic Notch Filter |
| LMF90CMJ/883 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4th-Order Elliptic Notch Filter |
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